A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications
C.-H. Jan, Uma Bhattacharya, R. Brain, S.-J. Choi, G. Curello, Garima Gupta, W. Hafez, Min-Seo Jang, Myounggon Kang, K. Komeyli, T. Leo, Nitin Nidhi, Li-Hua Pan, Jang Hyeok Park, Kinyip Phoa, Anisur Rahman, Chad Staus, Hiroyuki Tashiro, C. Tsai, Peter Vandervoorn, Li-Ting Yang, J.-Y. Yeh, P. Bai
2012 · 인용 310
A leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time. Low standby power and high voltage transistors exploiting the superior short channel control, < 65mV/dec subthreshold slope and <40mV DIBL, of the Tri-Gate architecture have been fabricated concurrently with high speed logic transistors in a single SoC chip to achieve industry leading drive currents at record low leakage levels. NMOS/PMOS Idsat=0.41/0.37mA/um at 30pA/um Ioff, 0.75V, were used to build a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages.
This technology offers mix-and-match flexibility of transistor types, high-density interconnect stacks, and RF/mixed-signal features for leadership in mobile, handheld, wireless and embedded SoC products.