Gate patterning by electron beam lithography using a tone reversal process (EB-R) highly compatible with the self-aligned double patterning process

Abstract By the electron beam lithography (EBL) process combined with the self-aligned double patterning (SADP) process, SiN hard masks (HMs) were successfully fabricated on a 300 mm wafer for a variety of gate lengths around 2x nm. The SiN is deposited by low-pressure chemical vapor deposition (LP-CVD) in the fine trenches with a bottom width of 18 nm in the tetraethyl orthosilicate (TEOS) layer etched by the EB resist mask drawn. After the selective SiN CMP on TEOS followed by selective TEOS etching, a 25 nm wide and 57 nm high SiN HM was successfully fabricated on a Si wafer, which will be replaced by an amorphous Si film for dummy gates.

Consequently, we have confirmed that an 18 nm wide and 71 nm high Si structure was fabricated by the subsequent etching using the SiN HM. Electron beam lithography using a tone reversal process (EB-R) is valid and useful especially for R&D stages of LSI devices due to the flexible pattern size design.