Impact of Line Edge Roughness on Device Performance: A Review

Abstract As semiconductor node technology advances to below 5 nm, it is vital to control Line Edge Roughness (LER) and Line Width Roughness (LWR). These factors are crucial for meeting performance, reliability, and yield goals. This study examines the primary causes of LER and LWR, including random patterning effects, the behavior of resist materials, and variations in the etching process.

Through root cause analysis using fishbone diagrams, we categorize contributing factors across lithography and plasma etching stages. A key insight of this work is the identification of mechanical equipment behavior, such as vibration, thermal instability, and gas flow fluctuations, as underexplored contributors to pattern roughness. By correlating literature data with known equipment failure modes, we highlight how mechanical-induced variability can propagate into nanoscale device features.

This study bridges the gap between process variability and equipment behavior, offering a new path toward predictive diagnostics and more intelligent control in next-generation semiconductor manufacturing. The insights presented here lay the groundwork for integrating process-aware metrology with equipment health data to improve performance at future technology nodes.