5.12 Tbps Co-Packaged FPGA and Silicon Photonics Interconnect I/O
Kaveh Hosseini, Edwin Kok, Sergey Shumarayev, Daniel J. W. Jeong, Allen Chan, Austin Katzin, Songtao Liu, Radek Roucka, Manan Raval, Minh Mac, Chia‐Pin Chiu, Thungoc Tran, Kumar Abhishek Singh, Sangeeta Raman, Yanjing Ke, Chen Li, Li-Fan Yang, Paulo Chao, Haiwei Lu, Fernando Luna, Xiaoqian Li, Tim Tri Hoang, Arnab Sarkar, Asako Toda, Ravi V. Mahajan, Nitin Deshpande, Conor O’Keeffe, Uma Krishnamoorthy, Vladimir Marko Stojanovic, Chris Madden, Chong Zhang, Matt N. Sysak, Pavan Bhargava, Chen K. Sun, Mark T. Wade
IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 2022 · 인용 27
Heterogenous co-packaging of optical I/O with compute, memory or switch nodes will deliver significant improvements in power, bandwidth and reach in data center and high-performance computing applications. A first-ever real-ized and validated 5.12 Tbps co-packaged FPGA with optical I/O is presented. The Multi-Chip Package integrates a 14nm FPGA die with five Ayar Labs TeraPHY™ optical I/O chiplets.