37.4 SHINSAI: A 586mm2 Reusable Active TSV Interposer with Programmable Interconnect Fabric and 512Mb 3D Underdeck Memory

As high-density 3D integration technology progresses, active TSV interposers are emerging as a critical component in More-than-Moore strategies [1],,[3], enabling the transformation of traditional multicore monolithic systems into compact two-layer stacking architectures. These active interposers, often referred to as base dies, typically occupy several hundred square millimeters and provide advantages, facilitating integrated power management, mature-technology-friendly system 10s, and efficient inter-chiplet communication through active buffers. Developing large-area silicon with TSV/bumping technology for dedicated designs is both costly and inefficient, analogous to reinventing the wheel.

Reusable 2.5D/3D components have emerged as a promising solution [4],, [6] to reduce the NRE costs and simplify the design complexity of 3D integrated systems. For example, a single active interposer can be configured in two different schemes [3]: one supports three CPU top dies, while the other operates with two domain-specific accelerators. However, the interconnect and interfaces are customized for specific chiplets in different configurations, leading to challenges in reusing signal links on the interposer.

Moreover, the expansive active area of the interposer allows for the integration of considerable on-interposer memory, known as 3D underdeck memory. However, the orchestration between the top dies and the underdeck memory poses challenges due to the diverse requirements across different tasks. To address these issues, this paper presents a reusable active TSV-interposer, known as SHINSAI, in 28nm-CMOS/TSV-middle/micro-bump (μbump) technology.

The key contributions are 1) heterogeneous dual-layer network-on-active-interposer (NoAI) with 512Mb underdeck SRAM; 2) programmable horizontal (2.5D) die-to die link (H-Link) fabric, achieving independent μbump-to-μbump routing for various interconnect topologies; 3) a reconfigurable vertical link (V-Link) bridging 3D NoC among the top and base dies, adaptable to varying up/down-stream bandwidth on stacked interfaces.