Development of Glass Core Build-up Substrate with TGV

In recent years, advancement of high-end servers and artificial intelligence technology, semiconductor chips sizes are becoming larger. however larger chips reduced yields. An alternative technology to this, Chiplet has been developing. Furthermore, it has been developed for heterogeneous integration with different functions on the one package.

Due to this technology trend, there is an increasing demand for larger semiconductor packages. Conventional packages assume that the issue of mounting accuracy arises due to the use of materials with a large Coefficient of Thermal Expansion (CTE). To solve this problem, there is a demand for flat core materials with excellent dimensional stability.

Therefore, development of build-up substrates using glass as a core material is required. To confirm the dimensional stability of the glass core substrate, we investigated the positional accuracy. Glass core could be reduced 35 % of positional accuracy variation compared to the organic core.

In addition, the warpage of glass core substrates is smaller than that of organic substrates. It was confirmed that the dynamic warpage can be reduced to less than half. One of the issues with glass core substrate is that the inside of the glass occurs break (SEWARE) during dicing.

The cause of SEWARE is CTE mismatch build-up resin on glass substrate. It was found that SEWARE occurs near the interface of the glass substrate and build-up resin. In addition, we confirmed that stress on glass can be reduced by edge coating with resin, and it was effective to prevent SEWARE after 260 degree$C$reflow process.

We fabricated prototype sample of glass core substrate with Through Glass Via (TGV). We confirmed that it can be void free Cu fill plating of TGV, and then there was no delamination or cracking at the interfaces between the TGV and Cu redistribution layer (RDL). We confirmed reliability testing of this prototype sample.

Resistance fluctuation rate of the TGV daisy chain was within+/-10 %before against initial resistance value.