Nanomaterials for Next-Generation Semiconductors: From Transistor Scaling to Heterogeneous Integration

As silicon CMOS approaches the 10 nm gate-length ceiling, short-channel effects, escalating power density and interconnect RC delays erode the traditional performance–power–area dividend. Zero- to two-dimensional nanomaterials—quantum dots, carbon nanotubes, nanowires, graphene and transition-metal dichalcogenides—offer atomically thin channels, ballistic transport and widely tunable band gaps, and are therefore intensively explored to extend Moore’s law beyond pure geometrical scaling. This timely review synthesises experimental and theoretical advances reported from 2020 to 2025, benchmarks key figures-of-merit for logic, memory, interconnect and thermal-management applications, and highlights critical gaps between laboratory demonstrations and 300 mm fab transfer.

Sub-1 nm 2D gate-all-around nanoribbon FETs achieving 6 mV dec⁻¹ sub-threshold swing, carbon-nanotube vias sustaining >10¹² A cm⁻² current density and 0.3 V RRAM arrays with 10⁹ endurance cycles exemplify recent breakthroughs, yet wafer-scale uniformity, sub-400 °C BEOL thermal budgets and long-term reliability remain open challenges. A design-technology co-optimisation roadmap targeting the 1 nm node is proposed to guide material scientists, device engineers and EDA developers toward energy-efficient, heterogeneous integrated electronics.