Design of a Heterogeneous, Near-Threshold Computing VLSI Architecture for EnergyProportional High-Speed Computing

ABSTRACT: The insatiable demand for computational power in applications ranging from artificial intelligence and big data analytics to mobile and Internet of Things (IoT) devices is perpetually constrained by the power wall. Traditional Very-Large-Scale Integration (VLSI) architectures, optimized for peak performance, suffer from severe inefficiencies under dynamic workloads, leading to unsustainable energy consumption and thermal management challenges. This paper presents the design and analysis of Heterogeneous Energy-Proportional Computing (HEPCore), a novel VLSI architecture that synergistically integrates multiple low-power techniques to achieve high-speed computation while maintaining ultra-low power dissipation.

The HEPCore architecture is founded on three pillars: 1) A clustered heterogeneous multi-core fabric comprising high-performance (HP) and low-power (LP) cores with a unified memory system, enabling intelligent workload mapping; 2) Aggressive Near-Threshold Voltage (NTV) operation for the majority of the computational blocks, drastically reducing dynamic and static power; and 3) A finegrained, adaptive clock and power gating scheme managed by a reinforcement learning (RL) based power management unit (PMU) that ensures energy proportionality. The architecture was modeled and validated using a 28nm FD-SOI process technology. Post-layout simulations demonstrate that HEPCore achieves a peak performance of 128 GOPS (Giga Operations Per Second) while operating the LP cluster at 0.5V (NTV), consuming only 98 mW.

The HP cluster, activated on demand, delivers 512 GOPS at 0.9V, with a total SoC power of 1.2W. Compared to a conventional symmetric multi-core processor, HEPCore provides a 5.8x improvement in energy efficiency (GOPS/mW) for typical mixed workloads and maintains a computational throughput within 15% of a fully active highperformance system while consuming 67% less energy. This work establishes a holistic design paradigm for breaking the power-performance trade-off, paving the way for sustainable exascale computing and energy-autonomous intelligent systems.