Transistor-to-Package Thermal Simulation with Hotspot Mitigation by Decoupling

Physics-based thermal SPICE of nanosheets (NSs) and CFET integrated with finite element modeling (FEM) enables comprehensive thermal simulations from transistor level to package level. Self-heating in transistors contributes 2-9°C to the ΔT. The thermal impact of a hotspot is decoupled and accounts for 27%–53% of max ΔT (Tmax-ambient temperature).

The CFET induces 27%-25% higher max ΔT than NSs. The sensitivity of ΔT w.r.t. layer thickness provides insights for thermal solutions. Four approaches for hotspot mitigations are investigated, including dummy via in BEOL, AlN bonding oxide, thermal vias, and high-thermal-conductivity (κth) interlayer dielectrics (ILD) in the backside power delivery network (BSPDN), which can reduce max ΔT by 5%, 5%, 7%, and 23%, respectively.