Advanced Logic Scaling in the Angstrom Era

We review several of the key elements responsible for driving advanced logic CMOS scaling into the angstrom era. At transistor level, nanosheet (NS)-based devices are taking the center stage, with finFETs being replaced by single-level NSFETs [1-5] consisting of several vertically stacked NS per device. They enable better electrostatics control, allowing further gate length scaling, while also offering high design flexibility on the number or/and width of the stacked NS.

A careful balance between drive current vs. capacitance is, however, needed to avoid higher power consumption [2,3]. Non-destructive and statistically relevant low frequency noise characterization of NSFETs at 48nm contacted-poly (gate)-pitch (CPP), a technique typically in good agreement with bias-temperature-instability regarding trends [6], also confirms that interface and gate stack learnings obtained in simpler, larger MOS structures can still be applicable to these ultra-scaled devices [7]. Further ahead, NSFETs have the potential to evolve into 3D stacked configurations like the so-called complementary FET (CFET) which maximizes the active footprint by having different polarity NSFETs folded on top of each other [8].

Several integration schemes can be used to build CFET. While monolithic silicon (Si)-channel stacked devices are widely considered to be the simplest to start with [9-14], alternative approaches using bonding technology [9,15,16] offer particularly attractive prospects for stacking devices made of different channel materials and/or different crystal orientations, and possibly also varying NS dimensions. Noting, moreover, that channel mobility/strain enhancement knobs remain an important topic with continued scaling, increasingly challenging also from a metrology perspective.

Furthermore, and in view of the ongoing quest for both higher performance and more energy efficient devices, CFET may also allow a new opportunity for the co-integration of germanium (Ge)-channel FETs, which have long been considered a potential candidate for low supply voltage (V DD ) applications. For the actual implementation of these devices, adoption of backside (BS) power delivery network (BSPDN) [6,17-20] and BS processing may also offer some interesting engineering options to handle off-state leakage concerns as proposed, e.g., in [20]. BS processing may further help to introduce, by using the wafer’s BS and for increased system functionality, new transistor architectures and materials, e.g., to connect circuits defined on the wafer’s frontside (FS) FEOL to BS metallization [20-22].

BSPDN, besides helping to alleviate routing congestion on the FS (thus enabling increased logic density and new connectivity schemes (Fig.1)) also allows reducing the overall power consumption by bringing the power supply closer to the transistors with lower resistance BS interconnects. The corresponding IR-drop reduction can enable lower operating V DD , leading also to a power density drop and, as such, less generated heat. Overall, with chips becoming increasingly more compact and powerful, efficient thermal management and heat dissipation solutions have emerged as ever more crucial for maintaining their performance and lifetime [20,22,23].

BSPDN might help resolve some thermal issues, thanks to the possibility of having reduced thermal resistances for the remaining FS-BEOL layers and better lateral thermal spreading by the BS metal layers. However, a key concern lies with the thermal impact on the devices’ self-heating from the extreme thinning (or even full removal) of the Si substrate underneath the transistor level (Fig.2), which has so far also been acting as an effective heat spreader. Some examples of proposed thermal mitigation strategies, e.g., to alleviate hotspots arising locally, relative to the chip background, will be discussed, overall emphasizing the need for integration options to consider both electrical and thermal performance aspects.

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Figure 1