What Is "3 Nanometers" the Length Of? — Measuring a Chip's Name with a Tape Measure

The Headline "3-Nanometer Mass Production"

"Mass production begins for the 3-nanometer process." If you have ever skimmed semiconductor news, you have likely seen a headline like this. A few years later, "2-nanometer" appears, and the next numbers get even smaller. Most people know that the smaller the number, the more advanced the technology.

Yet what length is that 3? Is it a name given because there is a component with a length of 3 somewhere inside the chip? This article follows that single question. Semiconductor factories advance from one step to the next every few years with a new manufacturing method that makes components smaller, and this step is called a generation. To give the answer first, people used to measure that generation by actual dimensions inside the chip, and today that number is a name given to a generation.

For the explanation, we use an apartment. It is a home commonly called a "34-pyeong" unit in Korea. Pyeong is an old unit for measuring area, and 1 pyeong is about 3.3 square meters. However, if you exclude the balcony from a 34-pyeong home and add up only the floors of the rooms, living room, and kitchen, 34 pyeong does not come out. The indoor area written on the official documents, namely the exclusive area, is usually 84 square meters, about 25 pyeong.

That is because the number 34 includes the area calculated by dividing spaces shared by multiple households, such as stairs and hallways. This metaphor is borrowed from the everyday naming convention for Korean apartments and is not a fact derived from research. We will carry this home with us to the end of the article.

The number in a name and the number measured with a tape measure can be different. "3-nanometer" is like that too. Only, it goes one step further than the 34 of the apartment.

How Small Is 1 Nanometer

First, let's get a firm grip on the unit. A nanometer is 1 billionth of a meter. One slice out of 1 millimeter divided into 1 million pieces is 1 nanometer. Since the thickness of a single strand of human hair is roughly 0.1 millimeters, that thickness is around 100,000 nanometers. Lengths measured inside a chip are counted with this tiny scale.

The object measured with that scale is a transistor. A transistor is a tiny switch that opens and closes the path for electric current. How switches perform calculations is covered in the companion piece "A Transistor Is a Switch". Here, we look only at the size of the switch.

There is a length that is most frequently talked about in a switch. The channel is the path where the electric current passes inside a transistor. And the gate length is the length of the section where the gatekeeper that turns the current on and off in the transistor pinches down on the channel.

Moving to an apartment analogy, the gate length corresponds to the dimensions of a single room measured with a tape measure. The question now shifts to: "Is the 3 in 3-nanometer this tape measure marking, or is it a name like the 34 in a 34-pyeong apartment?"

When Numbers Were Dimensions

For the first few decades, making semiconductors smaller literally meant drawing every dimension smaller. Keeping the shape of the flat transistor the same, engineers drew finer lines by progressively shortening the wavelength of the light used to pattern the chip (DOI: 10.1149/ma2023-01291774mtgabs, conference abstract).

Each step from this era earned a name. A node is the name given to a generation of semiconductor manufacturing. The "3nm" in "3nm process" is precisely a node name. From its inception, the semiconductor industry measured technological progress by the actual physical dimensions, specifically the shortest gate length of a transistor. This is how a 2020 perspective article summarizes it (DOI: 10.1109/jproc.2020.2981715, perspective article). In those days, the number in the node name shrank right along with that physical dimension. It was a time when the size of a room measured by a tape measure and the name of the house moved together.

What each generation represented as a step was also fixed. The pace of the industry was to double the number of transistors packed into the same area with every single generational shift (DOI: 10.1109/iccd.2014.6974673).

How much do you need to shrink things to double the count? From here on, it is simple math. If you reduce both the width and the height to about 0.7 times their original sizes, the area of a single space becomes about 0.5 times as large. If the area is halved, twice as many fit into the same spot.

Even if you line up the node names appearing in the news these days—such as 7, 5, and 3—they each shrink by a factor of roughly 0.7. That just reflects the ratio between the names, not that the name is a physical dimension anymore.

Two Things That Followed When We Made Them Smaller

When we made them smaller, good things followed all at once. As a result of making them smaller, computing performance and energy efficiency improved exponentially, and computers moved from large, bulky machines to personal computers, and then again to mobile devices and the cloud (DOI: 10.1126/science.ade7656). Among the good things that followed when we made them smaller, two have names.

Moore's Law is the observation that the number of transistors packed into a single chip doubles every set period. Gordon Moore saw that period as 1 to 2 years, and at the same time saw the cost of a single transistor falling as well (DOI: 10.1126/science.ade7656). The semiconductor industry has used this trend as an indicator to look ahead, and there is also the assessment that as everyone moved in line with that pace, it became a self-fulfilling prophecy (arXiv:2205.15011, preprint).

The second is power. Dennard scaling is the relationship where the smaller you made transistors, the more performance went up without power consumption increasing by that same amount (DOI: 10.1109/ipdps.2008.4536223). This relationship was laid out by Dennard and colleagues in 1974. One paper notes that this relationship served as a guide for 40 years up to that point as the number of transistors packed into the same area and performance steadily rose (DOI: 10.1109/icsict.2006.306040).

Moving to an apartment complex, it looks like this. It was a time when rooms were divided smaller to put twice as many homes in the same building, but the electricity used by each individual home decreased so much that the electricity bill for the entire building did not increase significantly. In the past, just by making them smaller, transistors became more numerous, prices became cheaper, and the power burden did not increase much.

Power Trembles First

Of these three, the power side trembles first. This happens around the mid-2000s. Moving past the 45-nanometer node, power leaking while standing by without being used and the variations in characteristics from one transistor to another are counted among the two most important challenges (DOI: 10.1109/icsict.2006.306040). When components approach the level of several nanometers, a transistor becomes something far from an ideal switch, leaking a lot of current even when turned off (DOI: 10.1109/jproc.2012.2190155).

And the physical conditions that made Dennard scaling possible have nearly ended (DOI: 10.1109/ipdps.2008.4536223). Around that time, chip designers shifted direction toward increasing the number of cores instead of making a single core faster, and that shift was partly a response to the breakdown of Dennard scaling (DOI: 10.1145/2024723.2000108).

The task of making things smaller itself does not stop. However, in the subsequent period, along with shrinking the dimensions, the properties of new materials and increasingly complex transistor structures lift performance (DOI: 10.1149/ma2023-01291774mtgabs, conference abstract). The reason performance improves is no longer a single length. The node names shrink generation by generation even after that.

The name that has passed through generations like that is the current "3 nanometer". The dimensions set to match this generation are written in the industry's joint roadmap. The International Roadmap for Devices and Systems (IRDS) is a roadmap where the semiconductor industry and researchers look ahead and record what dimensions the transistors should be matched to for each generation. Following this roadmap, the industry's "3-nanometer node" has a gate length of 16 nanometers (arXiv:2007.14448, preprint). This value is not a direct measurement of a chip, but rather copied from the roadmap by a 2020 simulation paper. Other simulations targeting 3 nanometers and beyond also set the gate length to 14 nanometers or less (DOI: 10.1109/ted.2020.2987139, computer simulation). Either way, the gate length is several times longer than the number attached to the name.

The 3 in "3 nanometer" does not point to the length of any single component inside the chip. It is a generation number. The 34 in a 34-pyeong apartment is still the area of somewhere including common spaces. The 3 in "3 nanometer" is closer to just a name than that. The direction is also opposite. A 34-pyeong apartment has a name larger than the measured value, and "3 nanometers" has a name smaller than the gate length of the roadmap. The name is 3, and the gate length recorded by the roadmap for that generation is 16. The two numbers do not measure the same thing.

A Ruler You Can Use Instead of a Name

If the name no longer tells you the dimensions, what should we use to measure generations? The ruler that chip designers actually use is spacing.

Gate pitch is the distance from the gate of one transistor to the gate of the next, including the contact placed between them. Here, the contact is a small connection that hooks up wires to both ends of the transistor. It is close to measuring from one wall to the next, including the thickness of the wall. This value determines how many can be lined up side by side. The earlier simulation targeting 3 nanometers set this spacing to 32 nanometers or less (DOI: 10.1109/ted.2020.2987139).

A design study comparing two transistor structures for the 3-nanometer generation begins its comparison by setting fixed rules for the gate pitch, the spacing between metal wiring running over the transistors, and the height of a single basic circuit row (DOI: 10.1109/ted.2022.3178665, design-technology co-optimization simulation). These kinds of spacings are the values used when talking about the size of a generation.

There is also a way to add up all the spacings and state it as a single number. Transistor density is the count of how many transistors fit onto a chip of a given area. Translating this to an apartment building, it is how many households fit into a single building. The "doubling every generation" we saw earlier was also said with this density in mind (DOI: 10.1109/iccd.2014.6974673).

The ruler of density is likely to become even more useful going forward. Physical limits have begun to show in shrinking things further on a flat surface, and international roadmaps predict that starting in 2031, transistors will be stacked in multiple layers (DOI: 10.1109/jxcdc.2024.3482464). Stacking layers increases the number of transistors contained on the same floor area even if a particular linear dimension stays the same. This is like an apartment building with more floors fitting more homes onto the exact same plot of land. Exactly how much this increases is something researchers are actively investigating.

The perspective piece from 2020 that we saw earlier argued that the ruler of gate length has now lost almost all its usefulness, and proposed density as the new ruler in its place. This is a proposal to measure the progress of logic circuits that handle calculations, memory that holds data, and the technology that stitches multiple chips together into a single mass all at once (DOI: 10.1109/jproc.2020.2981715, perspective piece). To compare generations, we must ask about spacing and density instead of names.

Separately from this, a proposal was also made in 2014 to redraw the roadmap from the perspective of entire products like smartphones and servers (DOI: 10.1109/iccd.2014.6974673).

Reading a "2-nm Mass Production" Article

Now let's read a new article: "Entering Mass Production of the 2-nm Process." With what we just learned, we can ask three questions.

First, what is this 2 the name of? Since the gate length where the roadmap shrank from the previous 3-nm generation was 16 nanometers, there is no basis to read the 2 in 2-nm as a tape measure tick. If the name is not a dimension, there is no guarantee that two companies attaching the same name means the same dimension. It is like how you cannot compare the room sizes of two houses using only the name "34-pyeong apartment."

Second, how many fit into the same area? How much the gate pitch and wiring spacing have narrowed, and thus how many times greater the density is compared to the previous generation, is the ruler measuring the progress of this generation. If an article wrote down this number, it tells you more than the name.

Third, was the power checked separately? In the era when Dennard scaling was alive, making things smaller naturally came with power burdens not increasing. After that relationship nearly ended, you cannot read the fact that it became smaller as solving the power problem. Power is now an item that must be asked about separately and answered separately.

When you hear a name, you ask for a ruler. Just as someone who hears "34-pyeong apartment" asks, "How many square meters is the inside floor of the house?", when you hear "2-nm," you can ask, "What is the spacing between gates, and what is the number of transistors in the same area?"

Remaining Questions

Opinions are divided on whether Moore's Law has ended. One view holds that as making things smaller approaches its limits, Moore's Law is also coming to an end, meaning performance must be sought in software, algorithms, and hardware design, and those gains will be uneven and increasingly diminishing (DOI: 10.1126/science.aam9744), while another view holds that the trend of the density doubling with each node continues today, albeit at a slower pace than before (DOI: 10.1126/science.ade7656).

Where to Look Next

How "After Moore's Law — What a "Nanometer" Came to Mean" dives deep into the 16-nanometer gate length of the "3-nanometer" generation and what the industry began counting generations by next, following the papers. How the power wall changed chip design after the end of Dennard scaling is examined in "Why Did the Clock Stop at 4 GHz — Dark Silicon and the Power Wall". The direction of dividing chips into multiple pieces and gluing them together is covered in "They Chose Not to Make It One Chip — The Bill for Cutting It Apart".

Other articles in "Chips from Scratch" cover how transistors perform calculations as switches ("A Transistor Is a Switch"), how those tiny patterns are drawn with light ("Lithography — Painting Circuits with a Brush of Light"), and why moving data is slower than calculating it ("Fetching Is Slower Than Computing — The Memory Bottleneck and HBM").

Source Papers

• "(Gordon E. Moore Medal for Outstanding Achievement in SSS&T) Moore's Law Sustained by Non-Lithographic Technologies" (2023) — DOI: 10.1149/ma2023-01291774mtgabs — Miniaturization has moved from the era of reducing lithographic wavelengths to geometrically shrink planar transistors, through the "equivalent scaling" era of new materials and dimensions, into the "3D power scaling" era described by IRDS 2022 (conference presentation abstract).
• "A Density Metric for Semiconductor Technology [Point of View]" (2020) — DOI: 10.1109/jproc.2020.2981715 — From the beginning, the semiconductor industry has measured technological progress by the physical dimension of the transistor's minimum gate length, but this metric has become nearly useless today. Instead, we propose a density metric that captures progress in logic, memory, and packaging/integration together (perspective article).
• "ITRS 2.0: Toward a re-framing of the Semiconductor Technology Roadmap" (2014) — DOI: 10.1109/iccd.2014.6974673 — Moore's Law was the driving force that doubled transistor density with every technology generation (node). Because existing roadmap methodologies fail to capture the evolution of the entire industry, we propose new system-level drivers and new metrics.
• "Toward attojoule switching energy in logic transistors" (2022) — DOI: 10.1126/science.ade7656 — Moore observed that the number of components on an integrated circuit doubles every one to two years while the cost per transistor decreases. The trend of doubling density with each node continues today, though at a slower pace than its historical rate.
• "Moore's Law is dead, long live Moore's Law!" (2022) — arXiv:2205.15011 — The semiconductor industry has used Moore's Law as a predictive metric, and it became a self-fulfilling prophecy. As agreement grows that the original Moore's Law is faltering, we propose a quantitative revision (preprint).
• "Power efficiency in high performance computing" (2008) — DOI: 10.1109/ipdps.2008.4536223 — The physical principles of Dennard scaling, which allowed performance to increase without a corresponding increase in power consumption, have largely come to an end. We cover methods for measuring power in large computers.
• "Overcoming research challenges for CMOS scaling: industry directions" (2006) — DOI: 10.1109/icsict.2006.306040 — Dennard's scaling theory and Moore's Law drove density and performance improvements for 40 years. Beyond the 45nm node, standby power and variations in device characteristics are the greatest challenges, and we present three directions: material and structure innovation, three-dimensional stacking, and novel-principle devices.
• "Science and Engineering Beyond Moore's Law" (2012) — DOI: 10.1109/jproc.2012.2190155 — As components approach a few nanometers, electronic devices move away from ideal switches and leak heavily in the off state. We examine alternatives such as parallel manufacturing, design efficiency, functional integration, and novel principles.
• "Dark silicon and the end of multicore scaling" (2011) — DOI: 10.1145/2024723.2000108 — Since 2005, designers have increased core counts instead of single-core performance, which is a partial response to the failure of Dennard scaling. Multicore expansion is also bound by power.
• "Negative Capacitance Enables FinFET Scaling Beyond 3nm Node" (2020) — arXiv:2007.14448 — According to the IRDS, the industry's "3nm node" is the last FinFET node with a 16nm gate length (background statement in a TCAD simulation paper, preprint).
• "Opportunities in Device Scaling for 3-nm Node and Beyond: FinFET Versus GAA-FET Versus UFET" (2020) — DOI: 10.1109/ted.2020.2987139 — Targeting the 3nm node to meet a contacted gate pitch of 32nm or less, we set the gate length to 14nm or less and compared device structures using TCAD.
• "Optimization and Benchmarking FinFETs and GAA Nanosheet Architectures at 3-nm Technology Node: Impact of Unique Boosters" (2022) — DOI: 10.1109/ted.2022.3178665 — At 3nm dimensions, treating gate pitch, metal interconnect pitch, and cell height as fixed rules, we compared the two structures using a design-technology co-optimization framework.
• "Scaling Logic Area With Multitier Standard Cells" (2024) — DOI: 10.1109/jxcdc.2024.3482464 — Because physical limits are visible in in-plane geometric miniaturization, the IRDS predicts a shift to stacking transistors in multiple tiers starting in 2031. We evaluated the density improvement potential of 2- to 3-tier standard cells.
• "There's plenty of room at the Top: What will drive computer performance after Moore's law?" (2020) — DOI: 10.1126/science.aam9744 — As miniaturization approaches its limits and Moore's Law comes to an end, performance improvements must come from software, algorithms, and hardware design, and those gains are opportunistic, uneven, and subject to diminishing returns.