Why Did the Clock Stop at 4 GHz — Dark Silicon and the Power Wall

The Core Count Began to Rise Instead of Speed

In the 1990s and early 2000s, whenever CPUs changed generations, their operating speed noticeably increased. Then at some point that rise stopped, and the first digit in advertisement slogans was taken over by "how many cores." The clock is the speed of the beat at which the processor works, in other words the operating speed, and a core is a single unit inside the processor that receives instructions and performs calculations. The 4 gigahertz (GHz) in the title is a common designation pointing to the mid-2000s when consumer product clock displays stopped rising further, and is not a value from the paper cited by this article.

Designers turned in the direction of increasing the number of cores instead of raising the performance of a single core after 2004 (DOI: 10.1145/2324876.2324879). The conference edition of the same study wrote that turning point as "after 2005" in the same sentence (DOI: 10.1145/2024723.2000108). The year of transition is hard to pin down to a single year.

The widely spread answer about what stopped is "because Moore's law ended." This article follows the other side of that answer with literature. Transistors, in other words very small switches turned on and off with electricity, continued to increase on chips even after that ("A Transistor Is a Switch — A Tiny Faucet You Open and Close with Electricity"). What stopped was not the number of transistors, but power. However, a considerable portion of the figures circulating on this topic hold true only when specific process models, workloads, and architectural designs are assumed. A workload is the type of work given to a computer. If the assumptions change, the values change too.

The Explanation That "Moore’s Law Has Ended"

The most common explanation goes like this. Miniaturization—making transistors smaller—has hit a wall, making it impossible to add more transistors, and that is why performance has stalled. Moore's Law is the observation that the number of transistors packed onto a single chip doubles every fixed period (What Is "3 Nanometers" the Length Of? — Measuring a Chip's Name with a Tape Measure), and this explanation assumes that observation has ended. It is neat and intuitive, but only partially correct.

It is true that miniaturization has run into physical roadblocks. Transistors open and close the channel—the path for current between both ends—with a voltage applied to the gate sitting on top. As the gate length of a silicon transistor (CMOS), meaning the section where the gate grips the channel, approaches a limit around 10 nm (nanometers), three problems arise. Short-channel effects where the gate fails to properly block the shortened channel, soaring power density, and delayed signals in the wiring connecting transistors. These three eat away at the gains in performance, power, and area that were reaped every time things were made smaller (DOI: 10.54254/2755-2721/2026.ka30036).

Power is already right in the middle of the list of miniaturization hurdles. Power density is the power used per unit area of a chip. When transistors increase in the same area, power density rises unless the power used by each individual one drops by that much.

The Number of Transistors Kept Growing, but Power Stopped

The number of transistors you can fit on a single chip—that is, the transistor budget—has continued to grow ever since. The very purpose architects had in increasing the core count was "to leverage Moore's Law scaling" (DOI: 10.1145/2324876.2324879). They spent the increased transistors on turning them into cores. A study that actually tried to measure dark silicon in multi-core processors stands on the same premise. At the time that research was written, processor design had reduced the chip area that could be run at maximum clock speed "to continue performance evolution according to Moore's Law" (DOI: 10.5753/wscad.2015.14275).

The reason the area exists but cannot be run at maximum speed is power. The power budget allowed for a single chip has not gone up, while the power consumed by a single core has dropped only very slowly (DOI: 10.11591/ijece.v13i3.pp3079-3087). Since the upper limit stays the same and the cost per core does not drop as much as expected, the trend of increasing cores cannot be continued as it was.

At the root of this mismatch is the collapse of Dennard scaling. Dennard scaling is the relationship where, as you make transistors smaller, power consumption does not increase as much as performance goes up (What Is "3 Nanometers" the Length Of? — Measuring a Chip's Name with a Tape Measure). Textbook explanations say that what supported that relationship was voltage. When making transistors smaller, lowering the voltage together kept the power density mostly maintained, and during that time, making them smaller, more numerous, and faster was all possible at once. That relationship has broken.

The authors of the aforementioned scaling study view that the shift to multi-core itself was a partial response to the failure of Dennard scaling, and that the same failure could soon tie down even multi-core expansion (DOI: 10.1145/2324876.2324879). A 2016 power management study also starts from the same diagnosis. "Since the collapse of Dennard scaling, performance growth has mainly relied on core count expansion, but the challenge of chip power density still remains" (DOI: 10.1145/2897394).

The result of this is dark silicon. Dark silicon is the region on a chip that cannot be powered on because of the limit on power consumption. As miniaturization proceeds, this region appears on the chip and grows larger. This is because the power used by the circuits on the chip does not decrease as much as the miniaturization does. As explained in a pre-peer-review overview article, even if cores become smaller, power does not drop by that same fraction, so the number of cores that can be turned on simultaneously on a chip cannot increase by that much. The name brings to mind dark matter in astrophysics, but the darkness here is about power (DOI: 10.31219/osf.io/cq4nf). There is also literature that describes the same phenomenon by citing heat as a concurrent cause: "power and thermal constraints render a significant area of the chip unusable" (DOI: 10.3233/978-1-61499-882-2-242).

Why the Voltage Stops Going Down — Threshold Voltage and the Boltzmann Limit

For Dennard's relations to hold, the voltage must go down as much as the transistors get smaller. That voltage does not go down.

This warning is old. A 1981 paper that was shrinking transistors down to the 0.5-micrometer level already wrote this: 「It is difficult to reduce the applied voltage because small voltage terms, such as the built-in potential of the junction, are no longer negligible.」 The applied voltage is the voltage hooked up to the circuit, and the built-in potential is the voltage that spontaneously forms at the boundary between two zones with different properties, which is the threshold of the boundary that "A Transistor Is a Switch — A Tiny Faucet You Open and Close with Electricity" talked about. The same paper projected that shrinking the device dimensions just two times further would hit a fundamental barrier to miniaturization (DOI: 10.1116/1.571121). That was about 40 years ago.

The deeper reason lies in the threshold voltage. The threshold voltage is the voltage where the transistor starts to turn on when you apply it to the gate. To lower the voltage supplied to the chip, you must also lower the threshold voltage. This is because if the gap between the two voltages shrinks, the current that the turned-on transistor flows decreases and it becomes slow. However, lowering the threshold voltage makes the leakage current spike. The leakage current is current that leaks out even in the "off" state of the transistor, which, if you compare it to the faucet from "A Transistor Is a Switch — A Tiny Faucet You Open and Close with Electricity", is water dripping steadily even when you turn the faucet completely tight.

The reason why is explained by how steeply a transistor can be turned off. The subthreshold swing is a value that measures the steepness of turning off a transistor, and is the gate voltage needed to reduce the current to one-tenth on the turning-off side. In the unit mV/decade (millivolts per decade), a millivolt is one-thousandth of a volt, and a decade is a single order of magnitude where the current changes tenfold. The smaller this value is, the more the current drops significantly even with a tiny drop in the gate voltage, turning it off cleanly.

The current leaking from a turned-off transistor mostly comes from electrons crossing over the boundary's threshold. Electrons at room temperature move with different energies because of heat, and among them, only some with energies higher than the threshold cross over. Raising the threshold with the gate voltage reduces the electrons crossing over, but how fast they drop is determined by the shape in which the electrons' energies are spread out according to temperature. That shape is called the Boltzmann distribution.

The Boltzmann limit is the lower bound that the subthreshold swing cannot drop below 60 mV/decade at room temperature in ordinary transistors where electrons cross the energy barrier via heat. It is also called the thermionic limit. Since temperature sets this lower bound, it does not drop just by making transistors smaller.

This lower bound is confirmed repeatedly in different devices. When bilayer graphene transistors are analyzed through calculations that simultaneously solve electronic structures and electric fields, the subthreshold swing gets stuck way above the room-temperature Boltzmann limit of 60 mV/decade. The authors wrote that that value was much lower than the experimental values up to that point, leaving room for improvement through technology (DOI: 10.1063/1.3364142). Interlayer tunnel transistors also reach the conclusion that "they cannot go below the 60 mV/decade thermionic limit" (DOI: 10.1142/s1793292017500692), and even in analytical models of junctionless cylindrical transistors, reducing the subthreshold swing by lengthening the gate length shows that "it cannot be reduced below the fundamental limit" (DOI: 10.1149/ma2016-01/16/995).

To summarize, the chain connects like this. For normal operation where electrons cross the threshold via heat at room temperature, even when the swing is at its best at 60 mV/decade, lowering the threshold voltage by 60 millivolts increases the off-state leakage tenfold. Since the swing cannot be lowered below that, the leakage cannot be reduced below a certain floor at the same threshold voltage. To keep it tied down enough to handle the leakage, you cannot lower the threshold voltage further, and thus you cannot lower the supply voltage further. This is the backbone of why voltage scaling stopped.

Leaking Power and Trapped Heat

The result is a reversal in the power mix. Dynamic power is the power used when turning transistors on and off, and static power is the power leaking away while they are off. As miniaturization progressed, static power became equal to or greater than dynamic power. One circuit design review summarizing this writes that gate leakage and subthreshold leakage "cannot be resolved with MOS structures or by introducing new materials." The same paper also offers paths forward. These are biasing techniques like MTCMOS and VTCMOS that mix transistors with low threshold voltages where speed is needed and high threshold voltages where leakage must be reduced (DOI: 10.55041/ijsrem17236). Leakage is closer to a structural cost that must be divided and managed through design than a side effect that can be eliminated.

Leakage is also tied to temperature. A FinFET is a transistor where the gate wraps around three sides of a standing channel. When you model FinFET leakage analytically, the leakage power is extremely sensitive to process variations—the tiny differences that occur with every manufacture—making it vary greatly from die to die. A die is a single piece of chip cut out from a wafer, and this leakage difference in turn leads to large temperature differences between dies. Because temperatures also vary greatly within a single die, this study treats leakage as a function of die temperature (DOI: 10.1108/13565360910923188).

When power crowds into a narrow space, it creates hot spots, which are unusually hot, narrow spots on a chip. Heat flux is the amount of heat that must escape from a given area. One 2009 thermal management study reported that a combination of miniaturization, increased transistor density, and higher performance demands created "severe on-chip hot spots," with heat flux approaching and sometimes exceeding 1 kW/cm² (1 kilowatt per square centimeter) (DOI: 10.1115/interpack2009-89289). Because this value is the heat flux of a single localized hot spot, it should not be read as the average for the entire chip.

If You Can't Turn Them All On — Increase Cores, Adjust Voltage, and Mix Cores

For a chip with a fixed power budget, designers have chosen roughly five paths: increasing cores, adjusting voltage and frequency, mixing large and small cores, running near the threshold voltage, and turning on only the necessary circuits.

The first is multicore, which means putting multiple cores into a single chip. Since they could not raise the clock speed, they increased the count. This response postponed the problem rather than solving it. The shift toward parallel computing, where calculations previously done sequentially in a single line are split across multiple cores to be done simultaneously, was about 「roughly halfway」 there by 2014 (DOI: 10.1145/2618409). Even with more cores, under actual thermal constraints and the constraints of the work streams (threads) that a program can run simultaneously, the corresponding performance improvements do not appear (DOI: 10.17918/etd-6322). Still, there was something to be gained within the wall. When three scenarios—voltage and frequency scaling, operating core count scaling, and both adjusted together—were evaluated under power constraints using GEM5 simulations, the performance improvement was 33% to 67%, and the authors confirmed that adjusting the operating core count and the voltage and frequency together can boost performance (DOI: 10.11591/ijece.v13i3.pp3079-3087). Merely increasing cores does not make the power wall disappear, but there remains room to squeeze value out within the wall.

The second is the adjustment of voltage and frequency. Dynamic Voltage and Frequency Scaling (DVFS) is a method of lowering and raising voltage and frequency as needed from moment to moment. Here, frequency is the same thing as the clock. One policy that bundled the control of the core and uncore—meaning the chip's internal interconnects outside the core, the shared cache, and the memory—cut total energy by more than 47% while keeping performance degradation below 2.3% in a full system simulation of the PARSEC benchmark (DOI: 10.1145/2897394). A benchmark is a standardized bundle of tasks set to measure performance. GPUs are similar. By measuring the power of 19 kernels and 931 samples between 400 MHz and 1000 MHz (megahertz) on an actual GPU, building a prediction model, and combining this with existing performance prediction models, it was possible to find a frequency setting that saved an average of 13.2% in energy over default settings with less than 10% performance loss (DOI: 10.1145/3152042.3152066).

These figures are all values obtained on specific benchmarks, mostly through simulation or measurement on a single platform. DVFS does not solve the power problem; it divides and shares the given power.

The third is asymmetric and heterogeneous cores that mix fast cores and slow cores on a single chip. This structure was introduced with the phrase that it 「promises substantial power savings while delivering performance comparable to existing symmetric multicores」 (DOI: 10.1145/1647300.1658422). Real-world measurements are more subtle. In a case study measuring a single big.LITTLE structure heterogeneous processor with EEMBC CoreMark-Pro, when both cores were run at their respective maximum performances, the small core was more efficient across all workloads. When the clock of the large core was lowered to match the performance of the two cores, in 5 out of 9 workloads the large core was similar to or more efficient than the small core (DOI: 10.1145/3152042.3152065). The small core is not always efficient, and what you compare and under what conditions flips the conclusion.

To this is added per-core power gating, which is the method of cutting power to cores that are not in use. A study that managed sleep modes for each core by distinguishing workload types on the same family of heterogeneous platforms reported that efficiency improved by up to 37% compared to the authors' immediate previous study based on PARSEC, and by up to 110% compared to the default power management method (governor), while referring to its own stage as the 「dark silicon era」 (DOI: 10.37917/ijeee.20.2.24).

Running Near the Threshold Voltage and Turning on Only the Circuits You Need

The fourth path is bolder. Near-threshold computing is a method of running transistors with the supply voltage very close to, but slightly higher than, the threshold voltage. Because energy efficiency peaks when the supply voltage approaches the threshold voltage, there is an expectation that more cores can be fitted within the same power budget. Practical energy gains have also been confirmed across four test chips spanning commercial 32/22/14 nm processes (DOI: 10.3390/jlpea10020016). In a post-layout simulation assuming a 28 nm FD-SOI process, it is claimed that running a low-power core cluster at 0.5 V (volts) to deliver 128 GOPS (billions of operations per second) at 98 mW (milliwatts) improved energy efficiency by 5.8 times in mixed workloads compared to conventional symmetric multicore processors (DOI: 10.15680/ijirset.2025.1412108).

There is a price to pay. A survey summarizing this field notes that near-threshold operation increases parameter variation—meaning the degree to which characteristics scatter across transistors—raises failure rates, and degrades performance, while categorizing techniques to offset those problems (DOI: 10.1145/2821510). The lower the voltage, the more vulnerable transistors become to manufacturing variation and noise, and a separate design cost must be paid accordingly.

The fifth path is to turn on only the circuits needed at that moment and leave the rest dark if you cannot turn on everything. This is the idea of accepting dark silicon as a premise of design rather than a defect. The representative of this path is the dedicated accelerator, a circuit made to perform only one predetermined type of computation.

The power of specialization is immense. One ASIC accelerator for quantized neural network inference, published as a pre-peer-review preprint on TechRxiv, reports that its energy efficiency per classification is 30 to 50 times that of a conventional multiply-accumulate-based design in the same TSMC 40 nm low-power process (DOI: 10.36227/techrxiv.23681922). An ASIC is a chip designed for a single purpose, and a quantized neural network is a neural network that calculates by reducing numbers to fewer bits. The authors emphasize that there was no loss in performance, area, or accuracy, and that these results were obtained without voltage scaling or approximate computing. These figures are self-reported by the authors, so they should not be read as independently verified values. If the claims hold in the same process, the same function, and a different architecture, that difference alone amounts to tens of times.

How Severe Is Dark Silicon? — Different Assumptions for Every Number

The severity of dark silicon is estimated differently across studies, and the difference largely comes from assumptions.

The most widely cited estimate is the prediction from the scaling study mentioned earlier. At 22 nm, 21% of a fixed-size chip must be turned off, and at 8 nm, that proportion exceeds 50%. Here, 22 nm and 8 nm are nodes, which are names given to a generation of a manufacturing process (What Is "3 Nanometers" the Length Of? — Measuring a Chip's Name with a Tape Measure). The same study calculated that across the configurations they reviewed up to 2024, only an average 7.9-fold speedup is possible, which falls short of the goal of doubling performance every generation by about 24 times (DOI: 10.1145/2324876.2324879).

This number comes with five layers of conditions attached.

1. There are two sets of process assumptions: predictions from the industry roadmap ITRS, and more conservative device scaling values.
2. The single-core model is a Pareto frontier built from measurements of over 150 real processors. It is the boundary connecting the processors that achieved the best performance at the same area or the same power.
3. It is a model where performance is set to the upper limit and core power is set to the lower limit. Both are the ends most favorable to the chip.
4. These are values for a fixed set of configurations: CPU-type and GPU-type, and symmetric, asymmetric, dynamic, and composite configurations.
5. They are values calculated from a fixed set of parallel workloads.

Remove the conditions and these numbers lose their meaning.

Different methods paint different pictures. One study used an exploration tool instead of a prediction model to filter out and estimate the amount of dark silicon in actually manufactured multicore processors (90 nm to 22 nm processes). This study defined dark silicon as the chip area that must be constrained to a low frequency, taking as its premise that the amount varies depending on the process used (DOI: 10.5753/wscad.2015.14275). Another study relies on Amdahl's Law—the principle that if a part of a task cannot be divided for parallelism, there is a limit to how much faster a chip can get simply by adding cores—by layering on reliability issues and memory bottlenecks, and it searches for voltage and frequency scaling strategies while treating "different amounts of dark silicon" as input values (DOI: 10.3233/978-1-61499-882-2-242). In this study, the dark silicon ratio is not a measured value, but an assumed one.

Long-term extrapolation models, estimates derived from real chips using tools, and analytical models all exist together, and each produces a different kind of number. Whichever ratio you encounter, the first question to ask is: which process node, which workload, and which model does this value belong to?

Is Specialization the Answer? — The Bill Sent to Accelerators

When you look at 30 to 50 times, the answer seems obvious. Specialization comes with a bill.

First, you give up versatility. The benefits of specialization come only from a fixed set of operations, and when workloads change, the hardware cannot keep up. That is why attempts emerge to change configurations at runtime. A preprint (SSRN, not peer-reviewed) discussing FPGAs, chips whose circuit configuration can be re-programmed later, points out that existing accelerators use bit-widths, degrees of parallelism, and clocks fixed at design time, failing to adapt to changing workloads (DOI: 10.2139/ssrn.6309151). It then reports that by using reinforcement learning to choose layer-by-layer configurations in real time, it achieved 3.2 times the energy efficiency (5.7 TOPS/W) compared to a static 8-bit baseline with less than 1.3% accuracy loss. Even if the reported gain is true, the burden of mounting a learning agent during execution remains. The authors claim this agent makes decisions in 45 µs (microseconds) and uses only 175 KB of on-chip memory—two orders of magnitude smaller than deep reinforcement learning alternatives—making it suitable even for resource-constrained embedded devices. The verdict depends on independent replication.

Second, idle accelerators also consume power. In applications with strict availability requirements, accelerators cannot be turned off or back on, wasting significant power even during low-load hours (DOI: 10.1007/s42452-025-07388-1). The same study produces a result through a preliminary simulation run on a virtualized radio access network (vRAN) that operating accelerators by pooling them beyond server boundaries can reduce the number of running units by up to 64.3% (compared to conventional intra-server sharing methods of 29.0%). The authors themselves state clearly that this gain is limited in applications where utilization is always high, and is large in places with regional load imbalances or time-of-day fluctuations.

Third, heterogeneity itself creates new instabilities. A study analyzing large-scale AI inference infrastructure argues that as accelerators of different generations, split serving paths, and virtualization layers mix together, instabilities arise from mismatches between layers rather than failures of individual components (DOI: 10.20944/preprints202603.1614.v1). It also points out that classical metrics like utilization, average latency, and tokens per second fail to capture these structural effects entirely because they view layers one by one. However, this paper is a preprint before peer review, and the authors explicitly state that their contribution is an analytical framework, not a prescription. What that paper has done stops at raising the problem.

Fourth, software debt remains. If even the transition to multicore was "halfway" in 2014 (DOI: 10.1145/2618409), it is safer to view programming models dealing with heterogeneous accelerators as lagging behind that.

How Much Can You Make from Cooling and Packaging?

If power is a wall, it feels like we should just pull more heat out. The achievements in this direction are significant.

On the data center side, there is an assessment that the demands of artificial intelligence and high-performance computing have pushed the thermal design power—namely, the power the cooling system is designed to handle—to the 10 kW scale. Beneath that, it is reported that a coral-inspired hierarchical embedded cooling structure handled a total package power of over 11 kW in an actual thermal test rig while keeping the maximum junction temperature below 90℃ (maximum heat flux of 377 W·cm⁻², peer-reviewed preprint) (DOI: 10.2139/ssrn.6464486). The junction temperature is the temperature at the site of the transistors inside the chip. Miniature thermoelectric coolers that cool local hotspots are constrained by the thermal resistance created by the act of attaching them itself (DOI: 10.1115/interpack2009-89289).

This gain is completely different depending on the size and shape of the device. Desktops and servers can mount heatsinks, heat pipes, and cooling fans, but mobile devices have narrow internal spaces and cannot use those methods. The criteria for judgment are also different. Because mobile devices touch human skin, the maximum case surface temperature rather than the maximum junction temperature determines thermal performance (DOI: 10.4071/isom-2012-wp34). The room to gain from cooling is large in servers and much narrower in handheld devices. As much as conventional heat dissipation components cannot be used, different kinds of solutions become necessary.

When cooling falls short, performance is trimmed. In a study testing software that adjusts workload according to temperature on two types of processors, one processor (AMD Ryzen 7 7730U) maintained temperature more stably after going through a cooling interval and automatic adjustment. On the other side (Intel Core i7-10750H), the temperature approached the 90–95℃ interval multiple times, leading the authors to write that adaptive control needs further refinement. Still, the authors' conclusion is that adaptive workload adjustment helps reduce the risk of throttling, which is when the chip slows itself down to prevent overheating (DOI: 10.36341/rabit.v11i2.8063). In embedded neural network inference, the price is more direct. When two image classification models were made to perform continuous inference on a commercial low-power CPU, latency constraints were met, but severe accuracy losses forced by thermal constraints were paid, and even reducing the model architecture did not prevent the temperature from hitting the threshold (DOI: 10.3390/jlpea10010010). In this research, the wall of power descended all the way to the accuracy of the answers the user receives.

Heat can even dictate design decisions themselves. Research on switching threads to which core in heterogeneous multi-cores within the thermal design power—namely, the power the chip can use without overheating—starts from the problem that DVFS, a common response, causes the system to fail to use its full performance instead of cooling the chip. This method achieved results 21% better than the previous technique (PCMig) while maintaining thermal safety (DOI: 10.1142/s0218126624502785). This means there is still performance left to recover even within the bounds where heat dictates decisions.

Has It Been Overcome Already, or Is It Still Dominant?

This conflict lives on inside the literature.

Some argue it is still dominant. A paper reviewing dark silicon (a pre-peer-reviewed preprint) writes that this problem brings about the end of the symmetric multi-core era, going so far as to say that the era of increasing core counts is 「coming to an end」 (DOI: 10.31219/osf.io/cq4nf). The tone of the literature points in the same direction. A 2018 study takes the situation where power and thermal constraints leave chip area idle as its starting condition (DOI: 10.3233/978-1-61499-882-2-242), a 2024 study calls its stage the 「dark silicon era」 (DOI: 10.37917/ijeee.20.2.24), and another study from the same year begins with the sentence that as cores increase, chip temperature rises and hurts performance (DOI: 10.1142/s0218126624502785). Their logic is that if the problem had been solved, there would be no reason for it to be presupposed over and over again.

Others argue it has been considerably alleviated. Near-threshold voltage operation promises to raise energy efficiency by several times (DOI: 10.1145/2821510), and test chips from three generations of commercial processes report that those gains scale well along with Moore's law (DOI: 10.3390/jlpea10020016). Specialization is reported to yield dozens of times more in the same process (preprint self-report) (DOI: 10.36227/techrxiv.23681922). They see that the amount of useful computation you can turn on within a fixed power limit has greatly increased.

The two sides are actually measuring different things. The former refers to the proportion of chip area that cannot be turned on simultaneously, while the latter refers to the amount of useful computation obtained with a given power. The former is a constraint still presupposed even in the late literature cited by this article. As for the latter, while there are reports that it has improved significantly, the basis for them consists of a survey's outlook, test chips from just a single company (Intel), and a preprint's self-report. The literature reviewed in this article lacks the data to judge which side is correct. The literature reviewed in this article contains no measured or estimated values for what the dark silicon proportion actually is in processes past 22 nm. That is why this article, too, does not state that number.

Things That Still Lack Answers

• We do not know the actual ratios beyond 22 nm. The widely cited figures of 21% and 50% or more are predictions looking ahead to 22 nm and 8 nm from the perspective of 2011–2012, and they are values based on fixed process models and workload bundles.
• The reliability cost of operation near the threshold voltage has not been quantified. Parameter variation and increased failure rates are problems highlighted by the survey (DOI: 10.1145/2821510), but there is no standard method to place that cost on the same scale as energy gains.
• We do not yet know whether there are exceptions to the 60 mV/decade wall. The Boltzmann limit has two premises: that electrons cross the barrier via thermal energy, and that the gate voltage moves that barrier by at most an equivalent amount. Tunnel transistors are devices intended to change the way they cross, but the interlayer tunnel transistor we saw earlier still failed to drop below 60 mV/decade (DOI: 10.1142/s1793292017500692). Negative capacitance devices are devices intended to change the share of the gate voltage affecting the channel. In a device that produced a negative capacitance effect using a film with ferroelectric-like properties, 45.06 mV/decade was reported within a ±1 V gate voltage range (pre-peer-review preprint) (DOI: 10.21203/rs.3.rs-77514/v1). In a two-dimensional material channel device, a figure of 6 mV/decade was included in a review as a recent breakthrough case. Whether it is measured or calculated does not appear in the abstract. The same review emphasizes that making them uniformly across a wafer and long-term use reliability remain unsolved, and asserts that there is a decisive gap between laboratory demonstration and 300 mm wafer mass production (DOI: 10.54254/2755-2721/2026.ka30036). Attempts to build channels out of materials just a few atoms thick are followed by "2D Semiconductors — Graphene's Betrayal and the Real Candidate for the "Post-Silicon" Era".
• The total cost of specialization has not been calculated. The energy gain of 30 to 50 times came from a preprint (DOI: 10.36227/techrxiv.23681922), and the design, verification, programming, and lifespan costs required to achieve it are not aggregated in the same units.
• The conclusions are tied to benchmarks. The figures cited in this article came on top of PARSEC, EEMBC, specific GPU kernel bundles, and specific image classification models. If the workload changes, the rankings can also change.

The Meaning of Performance Has Changed

Where the clock stopped, what actually changed is the meaning of the word performance.

The first sentence of a survey summarizing near-threshold computing compresses this transition. "Energy efficiency has now become the primary bottleneck to scaling performance across all classes of computing systems" (DOI: 10.1145/2821510). This means the bottleneck is energy efficiency rather than performance itself. The target of optimization has shifted accordingly. A study covering uncore frequency scaling policies moved its target from performance or power to performance per watt—in other words, the performance produced with the same power. This is to avoid saving a little power while losing a larger proportion of performance (DOI: 10.3390/s23031449).

What dark silicon left behind is this question. Transistors have continued to increase since then. However, because they cannot all be turned on at the same time, the design question has shifted from "how fast does it run?" to "what do you do with the given power?" The silicon left dark becomes room to choose what to turn on at any given moment.

This question has spread outside the chip as well. The thermal design power of data centers is heading toward the 10 kW scale (DOI: 10.2139/ssrn.6464486 — preprint), handheld devices have their performance determined by the temperature touching human skin (DOI: 10.4071/isom-2012-wp34), and inference run continuously on general-purpose embedded CPUs had to sacrifice accuracy due to thermal constraints in one study (DOI: 10.3390/jlpea10010010). The scales are completely different, but the grammar of the constraints is one. There is a power budget, and you must choose what to do within it. What began in the mid-2000s when clock ratings stopped rising remains the starting point even in the latest literature cited by this article.

Source Papers

Dark Silicon and the Collapse of Dennard Scaling

• "Power Limitations and Dark Silicon Challenge the Future of Multicore," ACM Transactions on Computer Systems (2012) — DOI: 10.1145/2324876.2324879 — Predicting unpowered portions exceeding 21% at 22 nm and 50% at 8 nm for specific parallel workloads, based on ITRS, two sets of conservative assumptions, and the Pareto frontier of roughly 150 processors.
• "Dark silicon and the end of multicore scaling," ACM SIGARCH Computer Architecture News (2011) — DOI: 10.1145/2024723.2000108 — The conference version of the above study. It identifies the same turning point as "after 2005," showing that even the timeline fluctuates.
• "Why is Silicon getting 'Dark'?" (2023) — DOI: 10.31219/osf.io/cq4nf (preprint) — Definition and causes of dark silicon (circuit power not dropping as fast as miniaturization), and the background of its naming.
• "Identificação Automática de Dark Silicon em Processadores Multicore," SSCAD (2015) — DOI: 10.5753/wscad.2015.14275 — Estimation in real multicore processors from 90 nm to 22 nm using an exploration tool. It assumes that values are process-dependent.
• "Reliability-Aware Voltage Scaling of Multicore Processors in Dark Silicon Era," Advances in Parallel Computing (2018) — DOI: 10.3233/978-1-61499-882-2-242 — Amdahl's law model plus reliability and memory overhead. It treats the amount of dark silicon as an input parameter.
• "Resource Sharing Centric DVFS for CMP Cores, Uncore, and Memory," ACM TODAES (2016) — DOI: 10.1145/2897394 — Diagnosis that the chip power density challenge remains even after the collapse of Dennard scaling. PARSEC simulation shows a 47% drop in energy.
• "Performance analysis of multicore processors using multi-scaling techniques," IJECE (2023) — DOI: 10.11591/ijece.v13i3.pp3079-3087 — An asymmetry where the power budget per chip has not increased, while power per core has decreased only slowly.
• "Efficient scaling of out-of-order processor resources" — DOI: 10.17918/etd-6322 — Under real thermal and thread constraints, increasing the cores does not yield a corresponding performance improvement.

The Physical Walls of Voltage, Threshold Voltage, and Leakage

• "Technology challenges for ultrasmall silicon MOSFET's," J. Vacuum Science and Technology (1981) — DOI: 10.1116/1.571121 — A 1981 warning that scaling down applied voltage is difficult due to small voltage terms such as built-in potential.
• "Intrinsic limits of subthreshold slope in biased bilayer graphene transistor," Applied Physics Letters (2010) — DOI: 10.1063/1.3364142 — The room-temperature 60 mV/decade Boltzmann limit.
• "Subthreshold Slope of Vertical Graphene Interlayer Tunnel Transistor," Nano (2017) — DOI: 10.1142/s1793292017500692 — Tunnel devices also cannot go below the 60 mV/decade thermionic limit.
• "A Comprehensive Analytical Study of Subthreshold Swing for Cylindrical GAA Junctionless FET," ECS Meeting Abstracts (2016) — DOI: 10.1149/ma2016-01/16/995 — Even with increased gate length, it does not drop below the fundamental 60 mV/decade limit.
• "Subthreshold Leakage Current Reduction Technique in Large Scale Integration with SRAM," IJSREM (2022) — DOI: 10.55041/ijsrem17236 — The inversion where static (leakage) power has become equal to or greater than dynamic power, with a strong statement that structure and new materials cannot solve it.
• "Analytical modeling ... leakage current and subthreshold swing factor of nanoscale double gate FinFET," Microelectronics International (2009) — DOI: 10.1108/13565360910923188 — Modeling leakage current as a function of die temperature, and sensitivity to process variation.
• "ZrO2 Negative Capacitance FET with Sub-60 Subthreshold Swing Behavior" (2020) — DOI: 10.21203/rs.3.rs-77514/v1 (preprint) — 45.06 mV/decade within a ±1 V gate voltage range. Pre-peer-review preprint (Research Square).
• "Nanomaterials for Next-Generation Semiconductors," Applied and Computational Engineering (2025) — DOI: 10.54254/2755-2721/2026.ka30036 — Soaring power density, and the unresolved gap between lab demonstrations of 6 mV/decade and mass production.

Architectural Responses — Multicore, DVFS, and Heterogeneous Cores

• "The Multicore Transformation Closing Statement," Ubiquity (2014) — DOI: 10.1145/2618409 — Diagnosis that the transition from sequential to parallel was "about halfway" as of 2014.
• "GPGPU Power Estimation with Core and Memory Frequency Scaling," ACM SIGMETRICS PER (2017) — DOI: 10.1145/3152042.3152066 — 19 kernels at 400 to 1000 MHz, averaging 13.2% savings with under 10% performance loss.
• "Maximizing Power Efficiency with Asymmetric Multicore Systems," Queue (2009) — DOI: 10.1145/1647300.1658422 — Early proposal that asymmetric multicore systems "promise" significant power savings.
• "A Case Study of Energy Efficiency on a Heterogeneous Multi-Processor," ACM SIGMETRICS PER (2017) — DOI: 10.1145/3152042.3152065 — When matching performance, large cores are comparable or more efficient in 5 out of 9 workloads.
• "Understanding Power Gating Mechanism ... in the Dark Silicon Era," IJEEE (2024) — DOI: 10.37917/ijeee.20.2.24 — Per-core power gating. A 37% improvement over the previous study and 110% over the default governor, based on PARSEC.
• "Thermal Safe Power Constrained Dynamic Mapping for Heterogeneous Multicore System," JCSC (2024) — DOI: 10.1142/s0218126624502785 — The critical awareness that DVFS trades cooling for an inability to fully utilize performance.

Near-Threshold Operation and Specialized Accelerators

• "A Survey of Architectural Techniques for Near-Threshold Computing," ACM JETC (2015) — DOI: 10.1145/2821510 — "Energy efficiency is now the primary obstacle to performance scaling." The trade-off of gains versus variance and failure rates.
• "Near-Threshold Voltage Design Techniques for Heterogenous Manycore SoCs," JLPEA (2020) — DOI: 10.3390/jlpea10020016 — Energy efficiency peaks near the threshold voltage. Practical gains across four test chips in 32/22/14 nm.
• "Design of a Heterogeneous, Near-Threshold Computing VLSI Architecture," IJIRSET (2025) — DOI: 10.15680/ijirset.2025.1412108 — 28 nm FD-SOI simulation, 128 GOPS at 98 mW at 0.5 V, with 5.8 times higher energy efficiency.
• "An ASIC Accelerator for QNN with Variable Precision and Tunable Energy-Efficiency" (2023) — DOI: 10.36227/techrxiv.23681922 (preprint) — 30 to 50 times the energy efficiency per classification compared to multiply-accumulate-based designs on the same TSMC 40 nm process. Pre-peer-review preprint (TechRxiv).
• "RLReconfigurer: RL-Driven Runtime FPGA Accelerator Reconfiguration" (2026) — DOI: 10.2139/ssrn.6309151 (preprint) — Limitations of design-time fixed parameters, achieving 3.2 times (5.7 TOPS/W) over static 8-bit. Pre-peer-review preprint (SSRN).
• "Accelerator pool: accelerator sharing architecture for energy efficiency," Discover Applied Sciences (2025) — DOI: 10.1007/s42452-025-07388-1 — Low-load waste in unstoppable accelerators, reduced by up to 64.3%, with limited gains in high-utilization applications.
• "SORT-AI: Accelerator Runtime Coherence in Heterogeneous AI Inference Infrastructure" (2026) — DOI: 10.20944/preprints202603.1614.v1 (preprint) — Inter-layer mismatch instability, uncapturable by classical metrics. It specifies being an analytical framework rather than a prescription. Pre-peer-review preprint.
• "Imitation Learning-Based Performance-Power Trade-Off Uncore Frequency Scaling Policy," Sensors (2023) — DOI: 10.3390/s23031449 — Why the optimization target shifted to performance per watt.

Heat, Cooling, and Their Limits

• "Effect of Thermal Contact Resistance on Optimum Mini-Contact TEC Cooling of On-Chip Hot Spots," ASME InterPACK (2009) — DOI: 10.1115/interpack2009-89289 — On-chip localized hot-spot heat flux approaching and exceeding 1 kW/cm², with thermoelectric coolers limited by attachment thermal resistance.
• "Energy-efficient thermal management of 11 kW multi-chip arrays ..." (2026) — DOI: 10.2139/ssrn.6464486 (preprint) — Over 11 kW of package power kept below 90℃ junction temperature in thermal test rigs, with a maximum heat flux of 377 W cm⁻². Pre-peer-review preprint (SSRN).
• "Thermal Power of Mobile Application Processor," ISM (2012) — DOI: 10.4071/isom-2012-wp34 — Mobile devices lack space for fans and rely on case surface temperature as the standard. The basis for differences across form factors.
• "Efficacy of Topology Scaling for Temperature and Latency Constrained Embedded ConvNets," JLPEA (2020) — DOI: 10.3390/jlpea10010010 — Thermal constraints force accuracy losses during continuous inference, and model reduction fails to control temperatures.
• "PENGEMBANGAN SISTEM AUTOMATIC WORKLOAD THROTTLING ...," Rabit (2026) — DOI: 10.36341/rabit.v11i2.8063 — Temperatures nearing 90 to 95℃ in two laptop-class processors, acknowledging the incompleteness of adaptive control.