They Chose Not to Make It One Chip — The Bill for Cutting It Apart

A Chip Made of 36 Pieces

In 2019, a research team designed and actually built and tested a chip made of 36 pieces. Its name is Simba. A single piece could deliver up to 4 trillion operations per second (4 TOPS), and the whole thing containing 36 pieces in a single package—the body that encases the chip and connects it to the outside circuitry—delivered up to 128 TOPS and up to 6.1 TOPS per watt. When feeding images one by one into the image recognition model ResNet-50, it processed 1,988 frames per second, and taking 0.50 milliseconds to process a single image (DOI: 10.1145/3352460.3358302, measured).

The sentence to note more than the performance is in the introduction of the same paper. A bundle containing multiple chips in one package is called a multi-chip module, and it states that multi-chip modules at the time of 2019 usually contained only a few large pieces, the reason being that communication between pieces consumes area, performance, and energy all at once. 36 pieces was not a natural choice. It was an experiment intentionally pushed to the extreme.

Then why cut them in the first place, and why doesn't just anyone go up to 36 pieces?

For a long time, the answer in semiconductors was one — the more a chip is made as a single piece, the better. That answer was overturned. We look in turn at what forced that overturn, and what bill was delivered in exchange for overturning it.

Because figures in this field are prone to mixing actually measured values, values calculated by design tools or thermal and cost models, and values announced by manufacturers introducing their own technology within a single paragraph, this article attaches the type to each figure in the sentences.

When You Cut It, a Cost Attaches to Every Boundary

That single line in the introduction, which made an exception for the 36 pieces, embodies the conventional wisdom. The conventional wisdom is closer to "cutting is a loss" than to "big chips are good."

First, consider the chip before it is cut. Chips are manufactured together on a wafer, which is a thin, round plate of silicon used to make chips ("Lithography — Painting Circuits with a Brush of Light"), and are cut out one by one after fabrication is complete. A single piece of silicon cut out this way is called a die. A monolithic SoC is a chip built by putting all the circuits needed for a system—compute, memory, input/output, and analog—together on a single die. Because there are no seams between circuits, signals travel the shortest possible path, but on the flip side, if a single spot goes wrong, the entire die can become unusable.

A chiplet is a separately manufactured piece of silicon that cannot function as a finished product on its own, and only becomes a single system when connected with other pieces inside a single package. Instead of making a chip out of a single die, it is divided and made into multiple pieces, then attached together in the final package.

The moment you cut it, something new is created. Within a single die, you can simply connect circuits with lines, but once it is divided into pieces, you must build separate devices at each boundary to send and receive signals. A die-to-die interface is a dedicated circuit and its protocol placed at both edges so that pieces sitting side by side in a single package can exchange data. The area this device occupies and the electricity it consumes are precisely the cost of cutting.

The place that records this cost most clearly is, ironically, a paper written to reduce that cost. Researchers who proposed a framework to jointly explore architecture and mapping—how to distribute workloads across which pieces—for a large-scale neural network accelerator, a chip built to speed up AI calculations, state the problem this way. Chiplet technology brings along higher packaging costs and an expensive die-to-die interface, and that interface consumes more area and power while offering lower bandwidth than the wiring inside a chip (DOI: 10.1109/hpca57654.2024.00022). Bandwidth is the amount of data that can actually be moved per unit of time ("Fetching Is Slower Than Computing — The Memory Bottleneck and HBM"). This sentence states the problem that the paper aims to solve, and the paper's conclusion will be seen later.

There are also calculated figures for that loss. A design platform study by a semiconductor company placed side by side the cases when the same system is built as a 2D monolithic chip—meaning a single die—versus being split and attached in three different ways. The three ways are a multi-chip module placing the pieces side by side on a package substrate, 2.5D placing them side by side on a thin silicon plate, and 3D stacking them vertically. The plate used in 2.5D is an interposer, which is a thin plate with multiple chips placed side by side and densely laid-out wiring connecting them in between ("The Bottleneck Was Never Compute").

In a high-performance/AI use case with a die area of 450 square millimeters, when the die was evenly split into equal pieces, the increased power compared to a 2D monolithic chip was 2.1% for the multi-chip module, 1.1% for the 2.5D silicon interposer, and 0.04% for the 3D stack. The area increased by 5.6%, 2.4%, and 2.4%, respectively (DOI: 10.1109/ectc51906.2022.00010). Because these values were calculated within the same paper under the same conditions, they can be compared with one another. However, these values were calculated by the design platform using a reference design, not measured from actually manufactured chips.

In this calculation, the shorter the distance between the pieces, the lower the cost of cutting. Power consumption decreased in the order of side-by-side arrangement, on an interposer, and vertical stacking, while the area overhead was the same for on an interposer and vertical stacking.

Up to this point is the conventional wisdom. Cutting is a loss, and that loss is greater the farther apart the pieces are. Yet, the industry cut them anyway.

Two Walls — Defects and Lithography Area

The first wall is defects. Yield is the ratio of usable chips produced among all made chips. Imagine a sheet of rolled-out bread dough with raisins scattered sparsely across it. If you stamp it out with a large cookie cutter, each piece is likely to contain a raisin; if you use a small cookie cutter, you only have to throw away a few pieces that happened to get a raisin. The defects on the silicon wafer are those raisins, and the size of the cookie cutter is the size of the die. The larger the die, the faster the probability of a defect landing inside it rises, and a single defect can render the entire die unusable.

The second wall is lithography area. Lithography is the process of shining light on a circuit pattern to transfer it onto silicon, and the plate containing that original pattern is the mask ("Lithography — Painting Circuits with a Brush of Light"). The industry also calls this mask, which is inserted into lithography equipment, a reticle. The reticle limit is the ceiling for the area that lithography equipment can print in a single shot. According to one foundry's announcement, the area printed by a single reticle is roughly 830 square millimeters, and any die larger than this cannot be printed in one shot.

A 2024 review summarizes the place where these two walls meet. Let us recall two terms from the review. A transistor is a tiny switch turned on and off by electricity, and a chip is countless such switches woven together ("A Transistor Is a Switch — A Tiny Faucet You Open and Close with Electricity"). The work of making transistors smaller is called scaling, and the name of the process generation given to each step forward in scaling is a node ("What Is "3 Nanometers" the Length Of? — Measuring a Chip's Name with a Tape Measure").

According to that review, as die size grew at an unsustainable pace, it ran into the reticle limit, and the rise in cost per single transistor is surpassing the gains in scaling previously won with each changing process generation (DOI: 10.1109/mm.2024.3524130, review). This means that even as scaling continues, the price per transistor has started to climb. Thus, "making it large as a single piece" becomes an accounting problem before it is a technical one.

Even so, it did not stop at 830 square millimeters. One foundry—in other words, a company that takes designs from others and manufactures chips—has been growing the plate itself on which the pieces are mounted, known as the interposer, by stitching together multiple exposure regions. According to an announcement where that foundry introduced its technology, the interposer grew from the size of a single reticle, about 830 square millimeters, to the size of two reticles, about 1,700 square millimeters, and then to the size of three reticles, about 2,500 square millimeters. This plate can accommodate a total of 1,200 square millimeters of logic chips and 8 High Bandwidth Memory (HBM) stacks (DOI: 10.1109/ectc32696.2021.00028, manufacturer announcement). HBM is memory placed right next to the computing chip to be used ("Fetching Is Slower Than Computing"), and a stack is a single mass formed by layering that memory tier by tier.

How much would the yield change if we cut it up? One analysis that redesigned commercial DRAM using a chiplet approach calculated those figures using DRAM as an example. DRAM is the memory that holds data while a computer is working ("Fetching Is Slower Than Computing"). In this analysis, the chip-level yield was 1.27 times that of a monolithic chip, and latency metrics improved as well. The cost figures in the same paper have a different denominator. In the upcoming process generation, the total cost decreased by up to 10% compared to traditional DRAM modules (DOI: 10.1109/tvlsi.2025.3527976). Because there are two baselines, we cannot lump this together into "improving by 27% and getting 10% cheaper." Moreover, these values came from an analysis that looked at devices, circuits, chips, and systems together, not from the measured cost of actually manufactured chips.

This calculation itself is not new. Already in 2009, one research institute built a cost model for 3D integration, compared the values of various stacking strategies with the single-die approach, and even accounted for the impact that through-silicon via technology and testing strategies have on overall system cost (DOI: 10.1109/3dic.2009.5306575, model). A through-silicon via is wiring created by filling holes pierced vertically through a chip with metal ("Fetching Is Slower Than Computing"). The question of whether dividing and attaching things brings an advantage has remained in the same place for over 15 years. In the meantime, the values and items put into the calculation have continued to change.

The plate on which the pieces are mounted also enters into the cost. A 2017 modeling study compared a 2D monolithic approach, a passive interposer laid out only with wiring, and an active interposer containing even circuitry. The conclusion was both. Both interposers can cost-effectively boost the functional yield and parametric yield of high-performance systems (DOI: 10.1109/iccad.2017.8203849, model). Functional yield is the ratio excluding defects that fail to operate at all, while parametric yield excludes even those defects that operate but fall short of performance standards.

What Followed After Cutting

If the reasons for cutting were yield and the reticle, something else was also discovered after cutting. This just might be the reason it stays relevant longer.

Heterogeneous integration is an approach where pieces with different properties and manufacturing processes are brought together in a single package without being unified under the same process. Computing circuits are made with the most expensive, latest-generation process, while circuits that handle power or communicate with the outside world are made with cheap, older processes and seated side by side. If they had been made as a single block, all of them would have had to use the most expensive process.

The reason for dividing is that not all circuits benefit equally from miniaturization. Reporting on a prototype where 96 cores—the units inside a processor that process instructions—were stacked in three dimensions on an active interposer, the researchers write the starting point of their design like this: because the costs of cutting-edge processes are rising, and analog circuits and input/output signal circuits are hard to shrink down, structures other than a single large die are becoming the mainstream (DOI: 10.1109/jssc.2020.3036341).

That prototype is a concrete example of heterogeneous integration. Six chiplets made with a 28-nanometer FDSOI process were placed using microbumps onto an active interposer made with a 65-nanometer process. The "nano" numbers attached here are the names of the process generations, and the larger the number, the older the generation ("What Is "3 Nanometers" the Length Of?").

A microbump is a tiny metal pillar with solder on its tip, sandwiched between two surfaces to connect chip to chip ("Nothing In Between — How Bonding Two Surfaces Directly Became the Center of the Process"). In this prototype, the pitch between the pillars was 20 micrometers. This is twenty times wider than the 1-micrometer pitch that will appear later, and actually making tighter intervals is covered in "Nothing In Between". The same paper measured the bandwidth density of the vertical connection as 3 terabits per second per square millimeter, and the signal propagation delay as 0.6 nanoseconds per millimeter (measured).

An article in which the same team presented the same prototype at a conference notes that even with complex functions included, the yield of the active interposer was high, and the reason was the mature 65-nanometer process and reduced complexity. A mature process is one that has been refined through long use. Complexity is recorded as the transistor density, which counts how many transistors fit into a given area ("What Is "3 Nanometers" the Length Of?"), and that value was 0.08 transistors per square micrometer. 30% of the interposer area was given over to capacitors used for voltage conversion—components that temporarily store electricity (DOI: 10.1109/isscc19947.2020.9062927). Thanks to the old process and lowered complexity, it was well-made. If it had been made as a single block, this circuit too would have had to be built with the latest process.

The same presentation paper also notes the limitations of the traditional approach, where a new name appears. A known-good die is a piece confirmed to be undamaged through preliminary testing before being attached to a package. If a single piece is defective, not just that piece is discarded, but the undamaged pieces already attached and the package along with them are thrown away. Therefore, filtering them out in advance before attachment determines the cost of the entire assembly.

The presentation paper points out the following: it is true that the traditional approach of dividing a system into multiple pieces and mounting them reduces costs through the known-good die strategy and yield management. However, those approaches are missing a way to easily incorporate flexible and efficient long-distance communication, seamless integration of different chiplets, and analog functions that do not scale well, such as power management or system input/output.

An article introducing a foundry's own 3D stacking platform places this concept in the same spot. That platform aimed to integrate known-good dies—differing in chip size, function, and wafer process node—into a single system chip, and cited three major challenges 3D packaging must overcome: heat, power delivery, and yield (DOI: 10.1109/ectc.2019.00095, manufacturer announcement).

This logic even changes the assembly sequence. A redistribution layer is a thin layer of metal wiring that reroutes and connects a chip's contact points to match the package-side wiring. An OSAT company—a company that packages fully manufactured chips and tests them—noted the reason it used a "chip-last" approach, where the redistribution layer is built first to verify quality before attaching the chips: losses from defective dies are reduced, and total production costs become lower. A package made that way contained one large chip designed for its specific purpose and eight small chiplets (DOI: 10.1109/ectc51906.2022.00309, manufacturer announcement).

So did it end up becoming cheaper? An OSAT company's presentation notes the following: Heterogeneous integration packages are more expensive than traditional packages that flip a single chip and attach it to a substrate (single-die flip-chip BGA). However, that increase is frequently offset by reduced total silicon costs and a shorter time-to-market for subsequent products (DOI: 10.4071/001c.129072, OSAT company announcement). "Frequently offset" is not the same as "always offset." The same presentation reveals that its company has been mass-producing the 2.5D approach using silicon interposers since 2017.

Reuse does not happen automatically either. Researchers who unveiled a reusable active interposer measuring 586 square millimeters describe the problem this way: making a new large silicon plate for every dedicated design is expensive and inefficient, and because the interposer's connections and interfaces are tailored to specific chiplets, it is hard to reuse the signal wiring on top of the interposer (DOI: 10.1109/isscc49661.2025.10904819). So they made the wiring programmable. There are similar points raised on the neural network accelerator side. Chiplets have been proposed as a way to spread the initial development cost across multiple products, but unless one carefully screens which chiplets are truly needed, opportunities for reuse will remain limited (arXiv:2510.08873v1, preprint).

The Bill for Gluing Them Together

10 times. This is the number cited as evidence that the cost of gluing them together has dropped. UCIe (Universal Chiplet Interconnect Express) is an open industry standard for die-to-die interfaces designed to bundle chiplets from multiple suppliers into a single package. A paper covering this standard notes that its low-power features bring a 10-fold power saving compared to conventional off-package input/output—that is, the method of sending signals outside the package (DOI: 10.1145/3665314.3680473, a figure stated while explaining the features of the standard, not measured). This means it is 10 times cheaper than sending signals outside the package, and it does not mean it is cheaper than simply connecting wires inside a single die. Therefore, it does not contradict the problem statement in the previous section that the area and power are larger than the wiring inside a chip.

There are also actually manufactured and measured figures. A two-chiplet processor built on a 7-nanometer process reported in 2020 communicated with each other via channels 0.5 millimeters long on an interposer. Altogether, they moved 320 gigabytes per second, with 8 gigabits per second per pin and a voltage swing of the transmitted signal of 0.3 volts. The energy required to move a single bit was 0.56 picojoules, and the bandwidth density was 1.6 terabits per second per square millimeter (DOI: 10.1109/jssc.2019.2960207, measured). A 4-nanometer FinFET die-to-die chiplet reported in 2023 operated at 32 gigabits per second per line, consumed 0.44 picojoules per bit, and delivered 8 terabits per second per millimeter of chip edge length (DOI: 10.1109/isscc42615.2023.10067477, measured). FinFET is a transistor structure built so that the gate wraps around three sides of the channel ("A Transistor Is a Switch").

Placing the two values side by side and reading them as "this much improvement has happened over a few years" is incorrect. They are different links made in different process nodes, and the latter two figures even differ in their units. 1.6 terabits is a value per area, and 8 terabits is a value per edge length. The only values of the same kind are the energy per bit of 0.56 and 0.44, and even those two come from different nodes. There are also pairs that are more confusing because their units are the same. The 3 terabits per second per square millimeter from the previous section is the value for a 3D connection stacked vertically, and the 1.6 terabits here is the value for a channel running flat across an interposer.

Therefore, this article sets a rule for comparison. To compare, it must be a control group within the same paper, or else the text must explicitly state what it is being compared against. This rule continues to be used in the subsequent sections.

A control group within the same paper looks like this. A design environment study by a back-end packaging company compared two boards under the same conditions that had two different widths of the UCIe specification—that is, the number of lines sent side by side at once. If you increase the width from x32 to x64 while maintaining the same transmission speed of 32 gigabits per second, you must shrink the redistribution layer's wire width and spacing from 2/2 micrometers down to 1.7/1.7 micrometers, and the wiring becomes much more complex (DOI: 10.1109/ectc51529.2024.00168, manufacturer announcement). The cost of doubling the bandwidth is billed in thinner wires.

Can this value keep shrinking all the way? The answer with the furthest-reaching outlook comes from the bonding pitch. The bonding pitch is the distance from the center of one contact point connecting chip to chip to the center of the immediately adjacent contact point ("Nothing In Between"). One research team reported a die-to-die solution across the entire range where the bonding pitch drops down to 1 micrometer.

There is one result in this paper that runs counter to intuition. As the authors' analysis suggests, contrary to the trend seen in conventional signal interfaces, the closer the bonding pitch gets, the better the energy-to-performance ratio becomes when you lower the frequency—that is, how often you change and send signals. And the authors conclude with this: their structure yields power, performance, and reliability characteristics that approach or surpass monolithic SoC designs as the bonding pitch approaches 1 micrometer (DOI: 10.1038/s41928-024-01126-y).

This sentence becomes false if you remove the conditional clause. "Chiplets beat monoliths" is not what this sentence says. At the extreme limit approaching 1 micrometer, according to the authors' analysis, that is the case. The pitch of the active interposer prototype we saw earlier was twenty times wider than that limit.

How Many Pieces Are Profitable?

The statement that 36 pieces was "an experiment deliberately pushed to the extreme" means that people do not usually go that far. If cutting is advantageous, is it even more advantageous to cut into finer pieces?

The cleanest answer came from a modeling study. It is a study that calculated how many pieces to divide the compute resources into—using performance per wafer as a metric—in a GPU with multiple chiplets contained in a single package, in other words, a processor that divides numerous calculations to run them all at once. Within that model, performance is highest with a few large pieces, cost and environmental footprint are lowest with many small pieces, and the best balance comes from using a moderate number of medium-sized pieces. The authors add two caveats: the optimal number of pieces varies depending on the workload, meaning the assigned task, and increases as the bandwidth between pieces grows (DOI: 10.1109/lca.2023.3313203, model).

This caveat means that the optimal number of pieces in this model is not a fixed constant. As the bandwidth between pieces grew, cutting more finely became optimal in this model.

Let us return to the 36 pieces that opened this article. The Simba researchers paid a real price for the fine division. To reduce the communication burden between pieces, they had to incorporate three tiling optimizations that placed data close to the pieces using it. What they gained from that was a speedup of up to 16% compared to their paper's baseline layer mapping (DOI: 10.1145/3352460.3358302). Software paid off part of the cost of the fine slicing.

Subsequent studies attempt to reduce this cost further. That search framework whose problem statement was quoted earlier co-optimized architecture and mapping, and reports achieving an average 1.98x performance and 1.41x energy efficiency compared to a combination of the Simba architecture with Tangram, an existing state-of-the-art mapping method, in its own computations. Instead, monetary cost increased by 14.3% (DOI: 10.1109/hpca57654.2024.00022). Another study that specialized chiplet accelerators while factoring in cost reports reducing the product of energy and delay by an average of 16% and 30% compared to Simba and NN-Baton within its own model (arXiv:2302.11256v3, preprint).

The three multipliers that just appeared each have different control groups and origins. The 16% is a value compared against its own baseline mapping by a paper on a prototype actually built and tested. The 1.98x, 1.41x, and 16%, 30% are values compared within their respective search frameworks, and the comparison targets also differ as "the combination of Simba with Tangram" and "Simba and NN-Baton," respectively. Placing these three in a single line and reading it as "chiplet design has advanced this much" is wrong three times.

A critique targeting the model itself also appeared in 2026. A preprint covering the modeling of the physical layer in chiplet simulation—the very bottom layer where signals are actually sent and received as electricity—points out that modern simulation tools often approximate links between chiplets with overly simplistic fixed-delay models (arXiv:2607.24221v2, preprint). A fixed delay model assumes that passing through a link always takes the same amount of time. Such simplification misses physical layer behaviors that vary during execution, such as fluctuations in the signal-to-noise ratio, interference between signals, clock jitter, iterations until error-correcting decoders converge on an answer, and packet retransmissions. The authors show that ignoring these effects distorts packet timing between chiplets and skews higher-level performance metrics like instruction throughput, leading to simulation results that stray off-trend.

What this critique targets is not the multiplier of an individual paper, but the way the simulator handles links between pieces. Earlier, it was said that these were not values measured with the same ruler; here, a question is raised about how accurate a single graduation of that ruler is.

The reason simulators simplify is that the design space is too large. When you combine the number and size of pieces, placement, connection structure, link bandwidth, and packaging technology, the candidates number in the hundreds of thousands, and an accurate simulator cannot sweep through all of them. Researchers who built a design space exploration tool for chiplet architectures wrote down that trade-off in numbers: compared to cycle-level simulation that tracks what a chip does at every single clock tick, they sacrifice 0.25% to 30.15% in accuracy to gain a speedup of 427 to 137,682 times (arXiv:2311.06081v2, preprint).

This is why tools keep appearing in this field instead of an answer key. One public tool created to guide decisions that must be made early in development, such as the number of pieces, partitioning method, and connection method, analyzed optimal chip size, defect density, testing cost, I/O types, assembly processes, and substrate choices on a case-by-case basis (arXiv:2503.15753v1, preprint). In 2026, a study also appeared that proposed a cost metric factoring in the duration during which a chip is actually operational and modeled how spare circuits widely used for yield and failure mitigation affect long-term cost-efficiency across two tiers: within pieces and between pieces (arXiv:2601.18159v1, preprint).

The very fact that tools continue to emerge is the answer. In the previous model as well, the optimal point shifted depending on the workload and the bandwidth between pieces. How many pieces are optimal is not yet settled, and may not be the kind of question that will ever be settled with a single answer.

The Bill Beyond Computation

A research team proposed redrawing the microbump layout of the UCIe standard. This is a layout already set as a standard. The values we have seen so far were items that could be put into calculations, such as area, power, performance, and cost. The reason such a proposal emerged lies in the items outside the spreadsheet that remain in an ecosystem where pieces from multiple companies are bought, sold, and glued together.

First is testing. When UCIe set the microbump layout as a standard, it included spare wiring to take the place of defective wiring. The team that studied testing and repair for this standard came up with a way to catch all hard and weak shorts and open defects in die-to-die wiring using just 16 patterns, no matter how many wires there are. A short is a defect where wires that should not touch are connected, an open is a defect where wires that should be connected are broken, and hard and weak refer to defects that are completely joined or broken versus those weakly so.

This team also proposes redrawing the layout to eliminate the risk of "fatal" defects that cannot be fixed even with spare wiring. And they write one heavy sentence: Because that restructuring is not compatible with the previous version's layout, it is best to reflect it in the standard as early as possible now (2024), while UCIe is still in the early stages of actual use (DOI: 10.1109/ets61313.2024.10567470).

The value of a standard comes from it becoming set in stone, but to fix a standard for the better, there are times when you have to break what has set. This tension hangs over the entire chiplet ecosystem.

Second, what needs to be standardized is not just electrical signals. To fit pieces from multiple suppliers into one package, what must the piece supplier hand over? The list written in a proposal tackling this question is as follows: a thermal model, physical model, mechanical model, input/output model, behavioral model, power model, signal and power integrity model, electrical characteristics, test model, and even documentation. Added to this as a newly needed item is security traceability assurance, which is guaranteeing that a piece has passed through a trustworthy supply chain. The authors also state their scope: the initial scope of this proposal is 2.5D interposer-based designs, and addressing the needs of 3D designs will require adding or modifying deliverables (DOI: 10.1109/3dic52383.2021.9687611).

Reality was lagging behind that. In 2023, an advanced packaging company wrote that die-to-die links for chiplet integration are mostly custom links that differ for each customer, creating boundaries in design and limiting the adoption of advanced packaging technology itself (DOI: 10.1109/ectc51909.2023.00176, manufacturer announcement).

So can you really attach someone else's pieces using a standard? That demonstration was reported in 2024. Different IP providers—meaning companies that sell circuit designs—demonstrated that silicon designed by them and made in different foundries can be housed together in a second-generation embedded bridge package and communicate with each other via UCIe (DOI: 10.1109/ectc51529.2024.00050, manufacturer announcement). The embedded bridge is the silicon bridge method we will see in the final section. However, an overview paper on this standard published the same year noted that to create an open chiplet ecosystem, standards for the next layer are still needed (DOI: 10.1109/mm.2024.3451532).

Third is trust. Assembling separately made parts also means having to ask where those parts have been. A team studying integrity checks for chiplet systems notes the risks as follows: the possibility of dies being swapped, and vulnerabilities where an interposer can be probed to spy on or tamper with them. Therefore, from a "zero trust" perspective of trusting nothing in advance, chiplets must not blindly assume they are operating in a friendly environment is their starting point.

They proposed a method to verify integrity by measuring the unique variance in the time it takes for signals coming from neighboring pieces to arrive, and measured it on dozens of commercial FPGAs—meaning chips whose circuits can be reconfigured—made by placing multiple dies on a silicon interposer. In a design with 144 cells, the average distance between values measured within the same device was 68.3 picoseconds, while between different devices it diverged to 847.7 picoseconds (DOI: 10.46586/tches.v2022.i3.391-412, measured data). Because values within the same device are close and those with other devices are far, the authors conclude that devices can be authenticated using this value. This means that if a die is swapped, it can be exposed by this difference.

Fourth are heat and mechanics. The problem of heat failing to escape is covered in depth by "Turn the Power Around and the Heat Gets Trapped — The Bill for Grinding Away the Silicon Under the Transistors", and the problem of board warping by "If the Board Warps, Nothing Above It Helps — The Bill for a Glass Base and In-Package Light". Here, we look only at the parts directly bearing on chiplet decisions.

On the heat side, there is a trade-off. In the design calculations earlier, the closer the distance between pieces, the lower the cutting value, but in a thermal model dealing with a structure featuring two chiplets placed on a 2.5D interposer, short intervals brought cooling difficulties to dense multi-chiplet integration. In the same model, connections attached directly without bumps were advantageous for removing heat (DOI: 10.1109/tcpmt.2022.3174608, thermal model). Neither value is from heating an actual package. On the actual product side, a 750-watt accelerator package has been reported, and that package was cooled by filling the gap between the chip and the heat dissipation component with a metallic material (DOI: 10.1109/ectc51529.2024.00391, manufacturer announcement).

On the mechanical side, there is a more direct irony: We cut up the large die to avoid it, but in trying to increase input/output and bandwidth, the package grew larger. An industry presentation covering the reliability of high-density fan-out packages—packages that spread wiring widely outside the chip—notes that as packages grow this large, package warping and reliability issues become more difficult. Warping is when a board made of overlapping different materials bends because the materials expand and contract by different amounts while heating and cooling, and the value stating how much a material expands when heated is the coefficient of thermal expansion ("If the Board Warps, Nothing Above It Helps").

According to the same presentation, the primary challenges for large packages exceeding 65 × 65 millimeters are warpage, the integrity of the redistribution layer, and package reliability. Different coefficients of thermal expansion among materials cause the device to warp, and the stress generated then can invite damage such as redistribution layer cracks. The package they covered contained one large chip made with a 7-nanometer process and 8 input/output chiplets (DOI: 10.1109/ectc51906.2022.00232, manufacturer announcement).

Even the Interposer Was Cut

2,500 square millimeters. This is the area of a silicon interposer scaled up to the size of three reticles by stitching together exposure fields. The plate carrying the pieces grew from one reticle to two, and then all the way there. In 2023, the foundry that made that plate described the problem like this in a presentation introducing the next structure: unprecedented interposer area created major yield and manufacturing challenges, and a way to push past the size limits of silicon interposers became urgently needed.

The answer they presented repeats this entire article once more. In the new structure, instead of a single monolithic silicon interposer, they use an interposer rewoven with several small local silicon connection chiplets and a redistribution layer bridging them widely across the top. According to the foundry's explanation, the local chiplets inherit sub-micrometer-thick copper wiring and through-silicon vias directly to maintain performance, while avoiding the yield loss that a single large silicon plate suffered (DOI: 10.1109/ectc51909.2023.00174, manufacturer presentation).

The same logic repeated itself one layer above. When they cut and pasted large dies, the plate built to mount them grew too large again, so they chopped up and reassembled that plate as well. As long as the reason for cutting lies in physics, cutting has no set final destination.

There is also a path of not making a large plate in the first place. The silicon bridge method embeds only silicon pieces small enough to bridge the gaps between pieces inside an organic substrate, which is a package substrate made of plastic-based materials. The need to make the entire plate out of silicon disappears, but stably embedding that bridge within the substrate manufacturing process becomes a new challenge (DOI: 10.1109/ectc32696.2021.00012, manufacturer presentation).

The perspective that does not view the interposer merely as a wiring passage is older than you might think. A 2014 study noted that the interposer connecting the memory stack and processor was using only a portion of its wiring capacity, and proposed expanding the communication network on the chip toward the interposer using the remaining wiring (DOI: 10.1109/micro.2014.61). The interposer is wiring that has already been paid for. The active interposers we saw earlier rest on the same idea.

Four Questions to Ask Before Choosing Chiplets

So there is no single answer to "Are chiplets better than monolithic?". What we can answer is a list.

① How large are the dies in this system? Defect density and the reticle limit make reasons to cut. If a die is small, the reason to cut it in the first place is weak.

② Do all circuits in this system want the same process? Analog and input/output circuits gain little from miniaturization. And the reason the single active interposer we saw earlier had a high yield was twofold: a mature 65-nanometer process and lower complexity.

③ Into how many pieces should it be divided? In one model, performance was highest with a few large pieces, cost and environmental footprint were lowest with many small pieces, and the optimum was somewhere in between. In that model, the optimal point shifted depending on the workload and the bandwidth between the pieces.

④ With what was that answer calculated? Most of the optimal points gathered in this article are values calculated for different control groups within different models, and a preprint has also pointed out that simulators often simplify links between pieces into fixed delays.

And there are things left outside the list. There is a proposal that to further increase the repair capability of redundant wiring, layout changes incompatible with previous boards are necessary; what needs to be standardized is not just electrical signals; and to buy and attach someone else's pieces, you must be able to trust those pieces. In one thermal model, the shorter the gap between pieces, the harder it was to cool them (in the same model, bump-free bonding was advantageous for removing heat), and the larger a package containing all the pieces gets, the harder warpage becomes.

All of these items are already written down as problems. Proposals to redraw the layout of redundant wiring have emerged, drafts of the list of models that piece suppliers must hand over have appeared, silicon from different foundries has actually communicated within a single package, and attempts to make interposer wiring programmable so it can be reused have also been reported.

Even so, optimism is conditional too. That sentence—stating that narrowing the bonding pitch down to 1 micrometer can approach or surpass monolithic—is true only with its conditional clause attached. What that conditional clause points to is ultimately "how densely can we attach them?", which is a different kind of problem from how small we make transistors.

Rather than a technology replacing miniaturization, chiplets have become a unit where assembly, alongside transistors, lifts performance. In the past, a single company could find the answer inside its own factory. Now, who made which piece in which process, whether those pieces speak the same language, whether they survive being attached, and even whether that piece is genuinely that piece have all become part of performance.

The decision not to make it as one was, in the end, also a decision not to make it alone.

Source Papers

• "Simba — Scaling Deep-Learning Inference with Multi-Chip Modules" (2019) — DOI: 10.1145/3352460.3358302 — Fabricated and measured 36 chiplets. 128 TOPS and 6.1 TOPS/W, with tiling optimization improving performance by up to 16%.
• "Gemini — Co-exploring Mapping and Architecture for DNN Chiplet Accelerators" (2024) — DOI: 10.1109/hpca57654.2024.00022 — Stated the problem that die-to-die communication has larger area and power overheads and lower bandwidth than on-chip interconnects. Compared to Simba+Tangram, it achieved 1.98x and 1.41x improvements with a 14.3% cost increase.
• "2.5D/3D Power and Signal Integrity Optimization for Chiplet Systems" (2022) — DOI: 10.1109/ectc51906.2022.00010 — Homogeneous partitioning of a 450 mm² die resulted in power increases of +2.1%, +1.1%, and +0.04%, and area increases of +5.6%, +2.4%, and +2.4% compared to a 2D monolithic design.
• "Disaggregated Design — Challenges and Enablers" (2024, review) — DOI: 10.1109/mm.2024.3524130 — Die size growth has hit the reticle limit, and the cost per transistor has surpassed scaling gains.
• "5th-Generation CoWoS-S with a 2500 mm² Silicon Interposer" (2021, manufacturer presentation) — DOI: 10.1109/ectc32696.2021.00028 — The interposer size grew from a single reticle of ~830 mm² to ~1700 mm² and ~2500 mm².
• "High-Speed and High-Capacity DRAM Modules Using Chiplet Integration" (2025) — DOI: 10.1109/tvlsi.2025.3527976 — Multi-layer analysis. Achieved a 1.27x yield improvement over monolithic designs and up to 10% cost savings compared to traditional DIMMs in emerging processes.
• "Impact of 3D Design Choices on Manufacturing Cost" (2009, model) — DOI: 10.1109/3dic.2009.5306575 — Compared the costs of various stacking strategies against a single die.
• "Cost-Efficient Design of Active and Passive Interposers" (2017, model) — DOI: 10.1109/iccad.2017.8203849 — Both approaches cost-effectively improve functional and parametric yields.
• "IntAct — A 96-Core Processor with 6 Chiplets on an Active Interposer" (2020, measurement) — DOI: 10.1109/jssc.2020.3036341 — Highlighted the difficulty of scaling down analog and I/O components. Achieved 3 Tbit/s/mm², 20 µm bumps, and 0.6 ns/mm.
• "A 220 GOPS 96-Core Processor on an Active Interposer" (2020, measurement) — DOI: 10.1109/isscc19947.2020.9062927 — Conference edition of the same team and prototype. The high yield of the active interposer is attributed to the mature 65 nm node and a density of 0.08 transistors/µm².
• "SoIC for 3D Heterogeneous Integration" (2019, manufacturer presentation) — DOI: 10.1109/ectc.2019.00095 — Integrating Known Good Dies (KGD) of varying sizes, functions, and nodes into a single system. The three major challenges of 3D integration are heat, power delivery, and yield.
• "Chip-Last FOCoS for Chiplet Integration" (2022, manufacturer presentation) — DOI: 10.1109/ectc51906.2022.00309 — Chip-last integration reduces defective die loss and total production cost.
• "Trade-offs in Chiplet and Heterogeneous IC Packaging" (2025, outsourced semiconductor assembly and test presentation) — DOI: 10.4071/001c.129072 — Heterogeneous packages are more expensive than single-die FCBGA, but silicon cost savings and faster time-to-market often offset this difference. The company's 2.5D TSV has been in mass production since 2017.
• "SHINSAI — A 586 mm² Reusable Active TSV Interposer" (2025) — DOI: 10.1109/isscc49661.2025.10904819 — Interconnects are tailored to specific chiplets, making signal link reuse difficult.
• "Mozart — Chiplet Ecosystem and Accelerator Co-Design" (2025) — arXiv:2510.08873v1 (preprint) — Without filtering out unnecessary chiplets, opportunities for reuse remain limited.
• "Energy-Efficient Chip-to-Chip Interface Design for Chiplets" (2024) — DOI: 10.1145/3665314.3680473 — UCIe low-power features reduce power consumption by 10x compared to conventional off-package I/O.
• "7nm Arm Core-Based CoWoS Chiplet Design" (2020, measurement) — DOI: 10.1109/jssc.2019.2960207 — 0.5 mm channel, 320 GB/s, 0.56 pJ/bit, 1.6 Tb/s/mm².
• "A 4nm 32Gb/s 8Tb/s/mm² Die-to-Die Chiplet" (2023, measurement) — DOI: 10.1109/isscc42615.2023.10067477 — UCIe standard compatible. 32 Gb/s/wire, 0.44 pJ/b, 8 Tb/s/mm beachfront bandwidth.
• "Unified Design Ecosystem for Chiplet Heterogeneous Integration" (2024, manufacturer presentation) — DOI: 10.1109/ectc51529.2024.00168 — At the same 32 Gbps, x64 requires 1.7/1.7 µm RDL, while x32 requires 2/2 µm.
• "Three-Dimensional System-in-Package Design Using UCIe" (2024) — DOI: 10.1038/s41928-024-01126-y — A continuum down to a 1 µm bump pitch. The authors' analysis suggests that as pitch decreases, lowering the frequency is advantageous, and approaching 1 µm brings performance close to or exceeding monolithic designs.
• "Balancing Performance, Cost, and Sustainability in Multi-Chip Module GPUs" (2023, model) — DOI: 10.1109/lca.2023.3313203 — The optimum is a medium size and a medium number of dies. The optimal number of pieces depends on the workload and increases as inter-die bandwidth grows.
• "Monad — Cost-Efficient Specialization for Chiplet Spatial Accelerators" (2023) — arXiv:2302.11256v3 (preprint) — Reduced Energy-Delay Product (EDP) by an average of 16% and 30% compared to Simba and NN-Baton.
• "DICE — Physical Layer Termination Modeling for Chiplets" (2026) — arXiv:2607.24221v2 (preprint) — When a simulator approximates links with a fixed delay, packet timing and IPC are disrupted.
• "RapidChiplet — A Chiplet Design Space Exploration Tool" (2023) — arXiv:2311.06081v2 (preprint) — Achieved 0.25% to 30.15% accuracy relative to cycle-level simulation while running 427 to 137,682 times faster.
• "CATCH — A Cost Analysis Tool for Heterogeneous Chiplet Systems" (2025) — arXiv:2503.15753v1 (preprint) — Case studies on optimal die size, defect density, testing cost, I/O types, assembly, and substrate.
• "A Lifecycle Cost-Efficiency Model for Multi-Chiplet Architectures" (2026) — arXiv:2601.18159v1 (preprint) — A cost metric that incorporates operational lifespan amortization.
• "Testing and Repair Improvements in UCIe" (2024) — DOI: 10.1109/ets61313.2024.10567470 — Detects all defects using 16 patterns regardless of the number of wiring lines. The authors note that map reconfiguration to eliminate unrepairable defects is not backward compatible.
• "A Standardization Proposal for Heterogeneous Chiplet Models" (2021) — DOI: 10.1109/3dic52383.2021.9687611 — Thermal, physical, mechanical, I/O, behavioral, power, integrity, electrical, and test models, along with documentation and security traceability. Initial scope is 2.5D.
• "Packaging Design Platform for Chiplets and Heterogeneous Integration" (2023, manufacturer presentation) — DOI: 10.1109/ectc51909.2023.00176 — D2D links are typically proprietary to customers, creating design boundaries that limit the adoption of advanced packaging technologies.
• "World's First UCIe Interoperable Silicon" (2024, manufacturer presentation) — DOI: 10.1109/ectc51529.2024.00050 — Demonstrated designs from different IP providers implemented on silicon from different foundries.
• "UCIe — The Standard for an Open Chiplet Ecosystem" (2024) — DOI: 10.1109/mm.2024.3451532 — Creating an open ecosystem still requires standards for the layers above.
• "Chiplet Integrity Verification Using Inter-Die Delay PUFs" (2022, measurement) — DOI: 10.46586/tches.v2022.i3.391-412 — Risks of die swapping, interposer probing, and tampering. Measured 68.3 ps within a class versus 847.7 ps between classes across 144 cells.
• "Thermal Modeling of 2.5D TSV Interposer Chiplet Packaging" (2022, thermal model) — DOI: 10.1109/tcpmt.2022.3174608 — Short pitches make cooling fine-pitch multi-chiplet integrations difficult.
• "3.5D Advanced Packaging for HPC and AI Accelerators" (2024, manufacturer presentation) — DOI: 10.1109/ectc51529.2024.00391 — A 750 W accelerator package utilizing hybrid bonding, a large silicon interposer, and a metal thermal interface material.
• "Reliability Challenges in High-Density Fan-Out Packaging" (2022, manufacturer presentation) — DOI: 10.1109/ectc51906.2022.00232 — Challenges beyond 65x65 mm include warpage, RDL integrity, and reliability.
• "Evolution of CoWoS Architecture for 2.5D System-in-Package" (2023, manufacturer presentation) — DOI: 10.1109/ectc51909.2023.00174 — The area of a 2500 mm² interposer creates yield challenges, leading to the replacement of the monolithic interposer with localized interconnect chiplets and global RDL.
• "Die Embedding Challenges in EMIB Packaging" (2021, manufacturer presentation) — DOI: 10.1109/ectc32696.2021.00012 — The method of embedding local silicon bridges into organic substrates and the challenge of embedding them reliably.
• "On-Chip Network Architectures for Silicon Interposers" (2014) — DOI: 10.1109/micro.2014.61 — Starting from the observation that interposers use only a fraction of their wiring capacity, this work proposes expanding the communication network using the remaining wiring.