After Moore's Law — What a "Nanometer" Came to Mean

The "3nm Node" in Quotations

A 2020 device simulation paper puts quotation marks around "3nm node" when writing it down as the reference generation. The same sentence immediately reveals the identity of that generation: according to the international roadmap (IRDS), the gate length is 16 nanometers, and it is the last FinFET generation (arXiv:2007.14448, preprint, TCAD simulation).

The mismatch where the name is 3, but the gate length written down for that generation in the roadmap is 16, was already traced by the primer "What Is "3 Nanometers" the Length Of? — Measuring a Chip's Name with a Tape Measure". As summarized there, a node is a name attached to a generation of semiconductor manufacturing, and the gate length is the length of the section where the gate, the gatekeeper turning the current on and off in a transistor, presses down and grips the channel. The value of 16 was also not obtained by someone measuring the gate of a 3nm chip with a ruler, but is the specification value written down by the roadmap for that generation.

The "last FinFET generation" in the same sentence points to the shape of the transistor. As the primer "A Transistor Is a Switch — A Tiny Faucet You Open and Close with Electricity" summarized, FinFET is a structure where the channel stands up like a fin so the gate wraps around three sides, and Gate-All-Around is a structure where the gate completely surrounds the channel from all four sides.

The primer stopped at the point saying, "To compare generations, you must ask about spacing and density instead of names." This article looks at what comes next. It is about why the name "3nm" and the specification of 16 nanometers drifted so far apart, what industry and researchers tried to count generations with after it became impossible to count them by a single length, and what changes when the yardstick is changed.

Most of the papers cited here are preprints (arXiv) before peer review, and a significant portion are values calculated inside computers rather than values measured by making actual chips. Therefore, so that the conclusion of a single paper is not read as an established fact, that fact has been written down in every spot where the load is heavy.

A Law Proposed for Rewriting

Moore's Law is the observation that the number of transistors packed into a single chip doubles at regular intervals (「What Is "3 Nanometers" the Length Of? — Measuring a Chip's Name with a Tape Measure」). One preprint evaluates that the semiconductor industry has used this observation as a forecasting metric to look ahead, and that while being used this way, Moore's Law became a self-fulfilling prophecy (arXiv:2205.15011, preprint).

A self-fulfilling prophecy is an event where the fact that a prediction exists moves people, ultimately making that prediction come true. The paper's assessment is that Moore's original speed of 「doubling every 1 to 2 years」 (a small value in the primer) came first, and as the industry used that speed as a forecasting metric and adjusted to meet it, that speed became reality.

The title of the paper is 「Moore's Law Is Dead, Long Live Moore's Law!」. The author writes that an increasing number of people agree the original Moore's Law has begun to shake, yet rather than discarding the law, proposes a quantitative revision. It is an attempt to more accurately predict where chip performance and energy consumption will head in the future, encompassing other laws that have branched off from Moore's Law (arXiv:2205.15011, preprint).

The fact that a revision has emerged reveals the nature of Moore's Law. Laws of nature operate just the same whether people believe in them or not. According to this paper's assessment, Moore's Law was a prophecy that came true as the industry adjusted to meet it, and as more people agreed that the original law was shaking, proposals to rewrite it emerged. Viewed that way, Moore's Law was closer to a schedule the industry imposed on itself than a property of nature.

When the schedule encountered a wall, the paths this industry has walked down were twofold. This is the summary from an article that re-examines the history of digital electronics since the 1960s. There were cases where constraints and walls spurred an evolution that improved technical techniques, and cases where they spurred a break that changed the technology altogether. The same article also notes the thresholds a new technology must clear to push out a dominant technology. Performance must improve by at least a single digit, meaning tenfold or more, and the cost, space, power, and scalability must also align (arXiv:2206.03201). Evolution or a break—these two paths are the map for reading the rest of this article.

The Bill Was Not About Length

A 2025 study left a transistor's channel alone and changed only the shapes of the ends of the source and drain, which are the electrodes attached to both ends of the channel. They lined up sharp-tipped protrusions. As a result, a device with a channel length of 20 to 25 nanometers showed DIBL and other key metrics comparable to a device with a 70 to 80 nanometer channel using conventional electrodes (arXiv:2506.14156, measured thin-film transistors).

DIBL (drain-induced barrier lowering) measures how much the voltage on the drain side pulls down the barrier that was blocking electrons, and the larger it is, the less the gate reliably turns the transistor off. This device had a single-gate structure with only one gate, and the channel was an oxide semiconductor (IGZO) rather than silicon. The authors envision this design being particularly helpful for semiconductor technologies used in the back-end-of-line (BEOL) process. The back-end-of-line process is the step where metal wiring layers are stacked on top of the transistors after they have all been built.

The channel length is unchanged, yet short-channel effect metrics like DIBL came out looking like a 70-to-80-nanometer-class device. Length was not a performance name tag.

The reason this is possible lies in the bill of shrinking. Shrinking transistors uniformly by a fixed ratio is called scaling. For a long time, scaling was close to free. Shrinking by the same ratio meant more transistors and higher speeds, without a proportional increase in the power burden. This is the era that the primer "What Is "3 Nanometers" the Length Of?" summarizes under the name Dennard scaling. But once dimensions entered the nanometer regime, physics handed us a bill, and none of the items on it translate down to a single length.

The first item is leakage. The leakage current (「A Transistor Is a Switch — A Tiny Faucet You Open and Close with Electricity」), which is the current that leaks out even when a transistor is in the "off" state, grows larger as things get smaller. The short-channel effect is a phenomenon where the channel becomes so short that the gate can no longer sufficiently control it. The shorter the channel, the greater the aforementioned DIBL, and the worse the subthreshold swing, which is an index representing the efficiency of turning off a transistor (「Why Did the Clock Stop at 4 GHz — Dark Silicon and the Power Wall」). The protrusion electrodes from earlier revived the gate's control near the electrode tips. They pulled this off without relying on process-complicating structures like double gates or gate-all-around.

The second item is reliability. As the insulating film under the gate gets thinner, the insulation breaks down over time. The value obtained by converting that insulating film's thickness into the equivalent thickness of a silicon oxide film that yields the same effect is called the equivalent oxide thickness, and the results of investigating a FinFET with this value at 0.8 nanometers split into two paths. For devices with an area near 10⁻⁸ square centimeters, the lifespan matched the results for planar devices. This implies that the FinFET structure itself does not introduce new failure mechanisms.

However, in devices with even smaller areas, they failed to meet the 10-year lifetime specification against soft breakdown, which is the formation of a weak leakage path in the insulating film. Moreover, the authors concluded that if the equivalent oxide thickness becomes thinner than 0.8 nanometers, reliability is challenged due to high leakage current (arXiv:2402.00886).

The third item is variability. The smaller you make them, the more device characteristics scatter. What proved particularly problematic in FinFETs is the phenomenon where the edges of the fin ripple minutely. That alone makes the threshold voltage, the voltage at which a transistor starts to turn on, jagged and uneven from device to device.

Proposed in response to this is a structure where the fin is defined by epitaxy. Epitaxy is a method of growing crystals layer by layer to build up shapes. In statistical simulations, this structure reduced the threshold voltage variability coming from edge roughness by 90% and the overall variability by 59%. Yet the very next sentence in the same abstract notes the price. In this structure, you do not need to keep the fin width tightly bound because of gate control or variability, which can make the fins wider and therefore the circuit less dense.

The authors answer this problem directly. Wider fins enable taller fins, and if you carve multiple layers of device isolation steps into a tall fin, you can create transistors of different widths within a single fin. Thus, the authors write that even though the footprint of an individual device is about twice that of a FinFET, basic circuits like inverters or NAND gates can yield equal or higher circuit densities if the width-to-length ratio is 2 or more (arXiv:1604.04454, simulation). Even if a single device's area is 2x, the circuit density can be equal or higher.

The fourth item is contact. Contact resistance is the resistance that arises solely at the boundary when current crosses over from a metal electrode into a semiconductor channel (「2D Semiconductors — Graphene's Betrayal and the Real Candidate for the "Post-Silicon" Era」). If you calculate for triple-gate and FinFET devices with widths and heights of 4 to 24 nanometers, contact resistance accounts for a substantial portion of the total resistance in devices with gate lengths under 30 nanometers.

The main culprit lay beneath the spacer. A spacer is an insulating partition that keeps the source/drain and the gate apart. Poor electrostatic control—meaning the gate's ability to hold onto the charge inside the channel—directly beneath that spacer played a major part in the contact resistance. Once the channel cross-sectional area dropped below roughly 50 square nanometers, the contact resistance and its variability rose sharply (arXiv:1602.07545, calculation).

The four items depend on electrode shape, insulating film thickness and area, fin edges, and electrostatic control beneath the spacer. None of them reduce to a single node name.

What Do We Count Generations By?

Moore's Law counted transistors. When that alone became insufficient, answers emerged in three directions: those asking where the physical limits lie, those calculating the upper bound of energy efficiency, and those completely redesigning the metrics themselves.

Starting with the location of the limits, a 2015 presentation summarized the ultimate physical limits of scaling from both theoretical and practical perspectives (arXiv:1511.05956). However, because the published abstract is only a single sentence, it is impossible to know what values were obtained or how.

Those who attached values focused on energy. CMOS is the circuit method used by nearly all chips today, pairing two types of transistors with opposite properties. A study estimating the maximum energy efficiency of a CMOS microprocessor divides the places where energy leaks into three: transistor switching, interconnect capacitance, and leakage power.

The energy per operation for each item was derived by combining three things: first-principles calculations starting directly from Landauer's principle regarding the minimum energy required to erase information, existing estimates of related values, and hardware measurements. The result is 4.7×10¹⁵ FP4/J by geometric mean estimation. This is a value measured by how many 4-bit floating-point operations can be performed per joule (J), and is a point roughly 200 times more efficient than microprocessors at the time of that study (arXiv:2312.08595, preprint). Because it is a value combining various estimates through a geometric mean, it is not a goal with a arrival date written on it, but a team's calculation of roughly where the point beyond which we cannot go lies.

There are also proposals to swap out the metrics entirely. The starting point is a diagnosis: that existing performance metrics, including Moore's Law, fail to accurately describe the technological progress of the semiconductor industry. CLEAR, proposed by the authors, is an acronym for Capacity, Latency, Energy, Area, and Resistance, and applies to all three layers of devices, wiring, and systems (arXiv:1612.02898, preprint).

According to the authors, this metric accurately explains technological progress retroactively from the 1940s up to the time the paper was written, and empirical trends like Moore's Law and Makimoto's Wave become special cases of this universal metric. As for the future, they offer a prediction: electronic technology cannot keep up with the doubling speed of the CLEAR value, and board- and chip-level photonics—technology that carries signals with light—can continue the doubling of the CLEAR value every 12 months, according to the authors' outlook.

The revisions of the previous section and the comprehensive metrics of this section aim at the same spot. A single line of measurement can no longer explain this industry.

The industry has its own scale: the roadmap. A roadmap is a planning chart where the industry and researchers look ahead and write down target figures to meet for each generation ("What Is "3 Nanometers" the Length Of?"), and when target figures are written down, researchers grade their own devices against those numbers. The paper that opened this article states that its device satisfies the on-current and off-current targets of the IRDS (arXiv:2007.14448). On-current is the current that flows when a transistor is turned on, and off-current is the current that leaks when it is turned off.

A study calculating indium phosphide nanowires states that it satisfies the high-performance requirements of the ITRS, the predecessor to the IRDS (arXiv:2308.14045), and a study calculating two-dimensional channels begins its discussion with what is required to meet the roadmap targets (arXiv:2010.06867). All three are simulations, and all three use the tables written by the roadmap as grading sheets. What the self-fulfilling prophecy seen earlier might look like in practice is visible here. The table is written first, and researchers grade their own devices using that table.

If You Can't Measure It, There Are No Numbers Either

To build nanosheets, which are thin, plate-shaped channels, you must etch away from the side the silicon-germanium layer—a sacrificial layer placed to hold a spot that will later be removed. You must know how much has been etched to control the process, which requires splitting the wafer—the thin, round silicon disk used to make chips ("Lithography — Painting Circuits with a Brush of Light")—to look at its cross-section, and the split wafer must be discarded.

A method to measure this depth inside the production line without splitting was tested. Varying the etching conditions to scatter the depth in a device containing three sacrificial layers, two measurements were run together with machine learning. These are scatterometry (equipped with spectral interference), which reads shapes from the spectrum of light reflected back, and X-ray fluorescence.

The results are divided into two stages. Both methods succeed at extracting the average depth as a single number. However, to separately view the depth of each individual sheet using machine learning, cross-sectional transmission electron microscopy reference data is needed to train the model. The final sentence of the same abstract adds a layer. Combining traditional optical models and advanced algorithms with spectroscopic scatterometry spectra yielded results that matched the sheet-by-sheet reference data very well (arXiv:2201.04725).

At least in this branch, someone has split something open first behind the value called "several nanometers." As structures fold into three dimensions, the act of measuring dimensions itself has become a research topic.

X-ray methods provide three-dimensional images of integrated circuits but lack the resolution to see at the atomic level, while electron microscopy sees at the atomic level but has limited depth information. The technique filling that gap is multislice electron ptychography. It is an electron microscopy technique that reconstructs images through computation, achieving both a lateral resolution smaller than atoms and a depth resolution on the nanometer scale. When this technique was applied to a gate-all-around prototype device, distortions and defects were revealed at the interface of the 3D gate oxide wrapping the channel—that is, the boundary where two materials meet.

The numbers coming out of there meet the title of this article head-on. Silicon relaxed gradually the further it got from the interface, and as a result, inside that channel called 5 nanometers thick, only 60% of the atoms maintained the same structure as bulk silicon. Moreover, the roughness profiles of the top and bottom interfaces differed from each other. This is because the two sides underwent different processes.

Interface roughness strongly dictates how easily particles carrying electric charge move inside the channel—in other words, mobility ("2D Semiconductors"). Yet the authors write that quantifying this in such a tiny 3D structure was previously impossible (arXiv:2507.07265).

A single name like "5-nanometer channel" splits apart like this on the inside.

Same Dimensions, Different Geometries

As planar structures could no longer handle leakage, the industry changed how many sides the gate wraps around the channel. It moved from FinFET, which wraps three sides, to gate-all-around, which completely surrounds all four sides. Gate-all-around stepped onto the stage after the 3-nanometer node thanks to its ability to well suppress short-channel effects (arXiv:2304.08175), and a 2026 paper notes that this structure is entering mass production as FinFET's successor (arXiv:2603.21015).

There is a calculation that shows the share of geometry most clearly. TCAD is a design simulation that builds a device inside a computer and calculates current. Using this TCAD, three geometries were compared with their device parameters set identically. They were a solid thin-wire-shaped nanowire gate-all-around, a hollow tube-shaped nanotube gate-all-around, and a nanotube made with a dual gate.

The dual-gate nanotube boosted on-current by 62% over the nanotube and 57% over the nanowire, and its off-current, subthreshold slope, and on-off ratio (the ratio of current when on to when off) all improved. When comparing the nanotube and nanowire directly, the difference is even clearer. The on-currents were similar, but the nanotube's off-current was smaller by an order of magnitude and its subthreshold slope was nearly half (arXiv:2304.08175, TCAD simulation). Even when dimensions and parameters are kept the same, performance is split by geometry alone.

Why geometry determines value is visible at the atomic level. As devices descend below 3 nanometers, atomic-level structures and quantum effects come to dictate performance, yet there had been no multi-scale simulation framework weaving together atomic models and first-principles quantum calculations. One research group built an all-around interface between a semiconductor and an amorphous gate oxide at the atomic scale, ran large-scale first-principles calculations on an interface model containing up to 2,796 atoms, and connected it to commercial TCAD.

Interface states are electronic states that form at the boundary of two materials and trap charge. With that framework, two previously unnoticed origins of interface states were revealed, and it was confirmed that interface states vary depending on the channel's size, orientation, and geometry. The authors conclude that this analysis explains why the industry favors nanosheet channels (arXiv:2308.08101, first-principles calculation). That nanosheet preference can be explained by interface states is the authors' interpretation, and this is not a study confirming that the industry actually chose it for that reason.

Gate-all-around is not the final chapter either. In this structure, when the gate voltage is negative, a leakage was observed where the drain current significantly deviated from thermionic behavior—meaning ordinary operation where electrons cross a barrier using thermal energy. When tracing the origin with first-principles simulation, this leakage is tunneling leaking from the gate to the drain. Tunneling is a quantum phenomenon where electrons punch through a barrier without going over it, and here it is greatly amplified as the insulating barrier between the two poles is lowered by the voltage on the drain side (arXiv:2603.21015, first-principles simulation).

The authors write that knowing the identity of this leakage is essential for setting the scaling limits of gate-all-around and guiding device and material optimization to reduce off-current. In recent experimental measurements noted alongside in the abstract, the influence of radiation-induced defects grew larger in the negative gate voltage region and was largely negligible at positive voltages. The location of the limit also shifts along with the structure.

Paths to Further Reducing Gate Length

Attempts to reduce the gate length have also continued, and at the destinations of those attempts, names and dimensions drift further apart.

We return to the paper that opened this primer. This paper investigated a structure introducing ferroelectric negative capacitance to a FinFET using TCAD. A ferroelectric is a material that maintains an electrical polarity without an applied voltage and can change its direction, and negative capacitance is a phenomenon that magnifies the effect of the gate voltage through that property.

The conclusion is that this structure can be extended to the "2.1 nm node" and nearly the "1.5 nm node," which are two generations after the industry's "3 nm node." The node names are all in quotation marks in the abstract as well. For the intermediate generations, it notes that the on-current and off-current targets of the IRDS can be met at operating voltages lower than the target values. The authors add that further scaling might be possible if capacitance matching, which aligns the capacitances of the ferroelectric layer and the dielectric layer with each other, is improved (arXiv:2007.14448, TCAD simulation). What the authors picked as their next step is not reducing the gate length further, but matching the capacitances of the two layers.

The name "1.5 nm node" does not point to anything 1.5 nanometers long. It is the name of a generation divided by which structure met which target values.

The end of conventional channels was also questioned through atomic-scale calculations. Meeting roadmap targets requires good electrostatic control and high mobility together, but in transistors made with conventional semiconductors, these two largely conflict below a gate length of 10 nanometers. Therefore, scaling of conventional channels such as silicon, germanium, and III-V compounds is expected to end around a gate length of 12 nanometers. Switching to less-explored two-dimensional channels such as $HfS_2$ or $ZrS_2$ can produce high currents down to about 6 nanometers.

The conclusion is that when the dynamic doping transistor—a new transistor structure proposed by the authors—is combined with a high-mobility material, it can descend to a gate length of 1 nanometer with a single-gate structure while maintaining the on-current of high-performance CMOS. This structure also addresses the separate challenge of how to perform doping in ultra-scaled devices (arXiv:2010.06867, atomic-scale simulation).

Here, another scale appears alongside nodes. The gate pitch, which the primer "What Is "3 Nanometers" the Length Of? — Measuring a Chip's Name with a Tape Measure" chose as the ruler to use instead of names, is the interval including the contact placed from one transistor's gate to the neighboring transistor's gate. A proposal combining fork-shaped contacts, which split contacts into branches, and dynamically doped nanosheets showed that excellent device characteristics and inverter energy-delay characteristics are maintained down to gate pitches below 30 nanometers. This leaves room to reduce it by 10 nanometers more than nanosheet-based devices (arXiv:2203.06364, atomic-scale simulation).

There is also the path of changing the channel material. In first-principles quantum transport calculations, a gate-all-around indium phosphide nanowire with a gate length of 4 nanometers was able to meet ITRS high-performance requirements in on-current, delay time, and power dissipation. When tensile strain, which stretches the crystal, was applied to a 3 nm gate length device, the on-current increased by more than 60% (arXiv:2308.14045, first-principles simulation).

Strain is a lever already proven in silicon. It was introduced in the 1990s as a means to boost mobility and commercialized in the early 2000s. Research transferring this to two-dimensional semiconductors applied strain to single-layer $MoS_2$ transistors using a silicon nitride capping layer. With a low process temperature of 350 degrees Celsius, this method can be used alongside existing CMOS processes. The median on-current increased by up to 60% in devices with a gate only on the substrate side, and up to 45% in dual-gate devices.

The largest improvement appeared when both the channel and contacts were reduced to the 200-nanometer level, reaching a saturation current of 488 µA/µm. That is higher than any value reported up to that point at such a short contact pitch. Most of the gain came not from the channel, but from tensile strain lowering the Schottky barrier of the contacts—the energy threshold at the boundary between the metal and semiconductor. The figures are measured values, but this cause is the interpretation provided by the authors' simulations (arXiv:2405.09792, measurement + simulation analysis).

A similar shift occurred on the process side as well. What constrained how short and how accurately the gate length could be made in horizontal nanowire gate-all-around devices was the fact that the gate was defined by wet etching. One fabrication method shifted that constraint to the resolution of electron beam lithography, which patterns directly with an electron beam. In a device with a 150-nanometer gate length, a subthreshold swing of 38 mV/dec (millivolts per decade) was obtained, and this value came from liquid nitrogen temperature at 77 kelvins rather than room temperature (arXiv:1810.03359).

There are also cases where the scale itself wavers. In bilayer tungsten diselenide ($WSe_2$), holes—which are empty spaces left behind by missing electrons—carry current, and the inter-valley splitting that governs their flow, which is the energy difference between the two valleys of the energy band, is not a fixed material constant. It is tuned according to the stacking method, strain, pressure, and dielectric environment, and the authors specify that the value also varies depending on the level of electronic structure theory used for the calculation (arXiv:2606.08955, first-principles + analytical model).

Even so, one thing remained fixed. The minimum subthreshold swing stays near the thermionic limit of 60 mV/dec regardless of the number of layers. This limit is the lower bound for ordinary operation where electrons overcome a threshold using thermal energy at room temperature, and since temperature determines the lower bound, the liquid nitrogen temperature value mentioned earlier did not break this limit ("Why Did the Clock Stop at 4 GHz — Dark Silicon and the Power Wall"). And in the region where the splitting is small, biaxial strain alters valley occupancy to tune only the effective mobility and on-current, leaving the subthreshold swing right at the thermionic limit.

In this model's bilayer $WSe_2$ device, the off performance was tied to the thermionic limit, while the on performance moved independently through strain. At least here, the two cannot be called together by a single length.

Splitting and Stacking — Moving to an Entirely Different Scale

The third response does not touch the transistor at all. One is splitting. A large chip is divided into small pieces called chiplets and then put back together inside a single package. If made in one piece, a single small defect forces you to discard the entire chip, but dividing it into pieces increases the yield—the proportion of usable chips among those manufactured—and allows well-made pieces to be reused. Heterogeneous integration, mixing pieces made in different process nodes together, also becomes possible.

Cost advantages do not happen automatically. One quantitative cost model breaks down the benefits into yield improvement, chiplet and package reuse, and heterogeneity, and then states the condition that total cost decreases when an appropriate multi-chiplet structure is chosen (arXiv:2203.12268). The costs are also outlined. Even a review noting that chiplets are advantageous for cost efficiency and time-to-market lists interface standards, packaging, security, and software programming as remaining challenges (arXiv:2311.16417). The placement and connection of the pieces also dictate performance, and one framework that optimizes placement reduced communication costs between chiplets by 24.81% (arXiv:2308.01672).

Security also becomes a new problem. Chiplets become one on an interposer, a baseplate that mounts and connects multiple chips, but the defense measures of existing single chips (systems-on-chip) that prevented hardware Trojans, reverse engineering, and design theft do not fit this interposer-based integration. One paper proposes mixing chiplets with different functions to catch Trojans as an alternative, and preventing duplication using the logic redundancy inherently present in circuits, evaluating it on an FPGA, which is a chip whose circuits can be reconfigured (arXiv:2010.13155).

There were also stumbling blocks to breaking chiplets down into even finer pieces. The bottleneck that previous studies pointed to as preventing chiplets from being reduced below 100 square millimeters was the area consumed by protection circuits to prevent electrostatic discharge and input/output circuits. One circuit simulation study shows that those circuits can be greatly simplified in 2.5-dimensional and 3-dimensional packaging, opening a path to split them even finer (arXiv:2511.10760, circuit simulation). One review covering automotive chips notes that the silicon industry is moving into the chiplet era against the backdrop of "The Slow Death of Moore's Law," and views chiplets as one of several strategies still under consideration on the automotive side (arXiv:2406.00182).

The other is stacking. One conference talk views 3-dimensional integration, which stacks circuit layers vertically, as being rapidly adopted as scaling slows down. According to that talk, the magnitude of the benefit varies depending on the application, technology choice, and design, and 3-dimensional design becomes a matter of breaking down the silos of microstructure, circuitry, and manufacturing (arXiv:2005.10866, conference talk).

The most radical proposal is CMOS 2.0. Leveraging wafer-to-wafer 3-dimensional bonding and backside wafer processing, the proposal is to shift the CMOS roadmap from geometric scaling to densely stacking function-specific device layers as a heterogeneous 3-dimensional stack. It is a proposal to change the axis itself that node names pointed to. The proposers also outline the costs. There must be an architecture and design automation tool foundation suited to this technology, and reliability issues must be addressed separately (arXiv:2510.04535).

In the same direction, an oxide semiconductor transistor has been reported that achieved an on-current exceeding 1 mA/µm and a subthreshold swing of at least 63 mV/dec without post-treatment, using a process that creates the channel later (arXiv:2512.21330). Ultraviolet laser annealing of heating only the upper layer among stacked layers—a treatment using heat to refine materials—has the potential to become a key enabler of next-generation 3-dimensional integrated CMOS, according to one review (arXiv:2209.05337).

Viewed through the two branches seen earlier, this side is closer to a break. Yet papers covering this trend call what they do an extension of Moore's Law (arXiv:2203.12268) and a path continuing Moore's Law (arXiv:2308.01672). For a break to succeed, it had to simultaneously overcome at least single-digit performance improvements along with cost, space, power, and scalability (arXiv:2206.03201). What happens when chips are fragmented and attached inside a package is covered in "The Bill for Cutting It Apart". The achievements of these responses are not recorded at all on the scale of "nanometers".

Changing the Yardstick Changes the Answer

There have long been many candidates to replace silicon CMOS. Without a way to compare devices operating on different principles using the same yardstick, it is impossible to say which one is better.

That is why creating a yardstick came first. A 2013 review outlined the structures and principles of logic devices being reviewed by a research consortium, described a general methodology for consistently estimating circuit area, switching time, and energy, and even presented the results of comparing the devices using that yardstick (arXiv:1302.0244).

In the same year, a proposal emerged to construct that methodology differently. Here, the yardstick is the energy-delay product. The energy-delay product is the energy required for a single switch multiplied by the time taken for that switch. The reason for multiplying the two is that if you only look at energy, a slow device wins, and if you only look at speed, a device that consumes a lot of electricity wins.

The gist of the proposal is to calculate this value not from dynamic characteristics such as switching energy and time, but from the device's resistance and switching charge. The authors discuss the problem of applying this method to both charge-based devices and non-charge-based devices, and note that this approach suggests a path for performance improvement and a new realistic limit expressed by the Planck constant (arXiv:1308.4748).

In 2017, the latest results of this benchmarking arrive. The device models were improved, new devices were introduced, and the methodology was expanded to wiring-centric analysis and non-Boolean logic applications. Boolean logic is ordinary digital circuits where all calculations are a combination of two values, true and false, while non-Boolean logic is circuits that calculate in other ways.

In contrast to Boolean circuits, spintronic devices show the potential to outperform conventional CMOS in non-Boolean circuits based on cellular neural networks (arXiv:1711.04295). Spintronic devices are devices that handle information using a magnetic property called spin instead of the electron's charge. The abstract only states this much, and it does not say that spintronics loses in Boolean circuits.

Within the same benchmarking study, contrasting results emerged depending on the use case: Boolean circuits versus cellular neural networks-based non-Boolean circuits. The result on the non-Boolean side is also "the potential to outperform." At least in this benchmarking, before deciding what task to assign, it was hard to say in a single word which device is better. This is why the question "How many nanometers is it?" is most clearly lacking here.

Some technologies have gotten off the node ladder entirely. The idea of controlling semiconductor conduction with ferroelectrics appeared in 1963, but it was tripped up by low retention and the difficulty of CMOS process integration, and flash memory took its place. Although ferroelectric memory was commercialized using oxide ferroelectrics, commercial products based on lead zirconate titanate stalled at 130 nanometers due to manufacturing process challenges.

Scandium-doped aluminum nitride, newly discovered around the time that paper was published, reopened the game. The reason it opened is the low deposition temperature. At around 350 degrees Celsius, it can be used alongside existing CMOS wiring processes. A device combining this material with a MoS₂ channel showed an on-off ratio of about 10⁶, a memory window of 0.3 V/nm, and retention of both states up to 10⁴ seconds, and the authors note this as a new approach for embedded memory and in-memory computing (arXiv:2010.12062). Because even matching which device to which function is a challenge, a mixed-signal neuromorphic processor to test it was also built (arXiv:2410.15854).

There are also places where the most fundamental scale has been shaken. Ohm's law is both the basic framework of charge transport and the concept of "electrical scaling" itself, which has enabled the continuous advancement of modern CMOS, that has been upheld. Yet channels are entering low-dimensional regimes for the sake of performance. Atomically thin oxide semiconductors, two-dimensional van der Waals semiconductors, and one-dimensional carbon nanotubes are materials cited as strong candidates to extend Moore's law.

A 2026 study reports that in these materials, disorder-induced electronic localization—meaning the phenomenon where electrons are stuck in place due to disorder within the material—causes Ohm's law to break down and linear scaling in the lateral direction no longer holds (arXiv:2601.01283, preprint). This paper does not stop at signaling the wall. The authors built a quantitative model capturing the role of the disordered region, and with that framework consistently explained the experimental observations of atomically thin In₂O₃ transistors across channel length, temperature, thickness, and post-annealing conditions.

The relationship that doubling the length doubles the resistance was an absolute prerequisite for the scale called a "nanometer" to have meaning. Channels are entering a regime where that prerequisite does not hold, and a new language to describe that regime is now being forged.

The Habit of Counting Progress with a Single Number

Moore's Law has spread beyond semiconductors. There is an analysis asking whether quantum computing has something like Moore's Law. The author first notes a common belief. It is that many technologies progress according to exponential laws, and that quantum computing also joins that crowd to inevitably mature.

The basic unit that a quantum computer uses to hold information is called a qubit. The holy grail in this field is a machine with thousands of error-corrected logical qubits, where each and every one of those logical qubits is again built from thousands or more physical qubits. When it reaches that scale, molecular simulation or the factoring of a 2,048-bit RSA key becomes possible. "According to many predictions, within 15 years," the author writes, though this is not the author's own claim but a common belief cited for inspection.

The result of the inspection is this. Moore's empirical law does not easily translate into quantum computing. The reason is the same as what we have seen throughout this article. Qubits have multiple performance indicators, and they do not magically improve together just because a new manufacturing technique appears.

However, the author does not say that something like Moore's Law does not exist at all. Such a thing may be at work in supporting technologies like cryogenic cooling technology and control electronics, and algorithms, software, and engineering are also helpers of progress. At the same time, the author writes that the future of quantum computing depends in large part on qubit fidelity, which is the degree to which qubits compute without error, and that it is progressing quite slowly, especially when scaling up. The author also suggests that in the future, other metrics—such as the quality of the computed results and the energy balance of quantum computing—may enter the board and change the landscape (arXiv:2303.15547, preprint).

A single number represents the progress of an industry, and then the items that the number concealed come out one by one.

So What Did the "Nanometer" Become?

The slowdown of planar miniaturization is a fact. Leakage, reliability, variability, and contact resistance have all presented their bills together (arXiv:2402.00886, arXiv:1604.04454, arXiv:1602.07545), the awareness that absolute physical limits exist has taken root (arXiv:1511.05956), and the calculation of energy efficiency upper bounds has settled in (arXiv:2312.08595). Even so, attempts to squeeze out performance outside of shrinking lengths have not stopped. The stage has shifted to shapes where the gate wraps around the channel (arXiv:2304.08175, arXiv:2308.08101), to ferroelectrics, strain, and two-dimensional channels (arXiv:2007.14448, arXiv:2405.09792, arXiv:2010.06867), and toward splitting and stacking chips (arXiv:2203.12268, arXiv:2510.04535), and most of the work cited here is at the simulation and proposal stage. Answers are divided on whether Moore's Law has ended.

Here is what that shift did to the "nanometer." Where the name tag used to point, there are now multiple values. Gate length, gate pitch, interface state, the ratio of bulk-like atoms, subthreshold swing, and on-current all stand apart. Needing a name to call that multiplicity all at once, that name is "3 nanometers."

So the remark that "it is just marketing" is only half right. The international roadmap actually holds definitions for that generation (arXiv:2007.14448), and researchers use those definitions as a scorecard (arXiv:2308.14045, arXiv:2010.06867). The name tag is not a lie, but the name of a bundle, except the name does not tell you what is inside that bundle.

What Moore saw was the curve of transistor count. When the force pushing that curve tried to move from "getting smaller" to "geometry" and "integration," the response that emerged was neither to discard the curve nor to keep it, but to redraw the curve. There is a quantitative revision (arXiv:2205.15011), a comprehensive metric bundling five items (arXiv:1612.02898), benchmarking comparing different devices (arXiv:1308.4748), and findings showing that which circuit you measure in changes the direction of the answer (arXiv:1711.04295).

Next time you see the "nm" number of a new chip, you can recall two things together: that it is not a length measured with a ruler, and that a single scale to tell you what is contained in that spot has not yet been decided.

Source Papers

• "Moore's Law is dead, long live Moore's Law!" (2022) — arXiv:2205.15011 (preprint) — Self-fulfilling prophecy and amendments.
• "Technologies and Computing Paradigms…" (2022) — arXiv:2206.03201 (preprint) — Evolution or replacement, the threshold is single-digit.
• "Fundamental Limits to Moore's Law" (2015) — arXiv:1511.05956 (preprint) — Ultimate physical limits (one abstract sentence).
• "Moore's Law in CLEAR Light" (2016) — arXiv:1612.02898 (preprint) — The CLEAR composite metric and its 12-month doubling prediction.
• "Limits to the Energy Efficiency of CMOS…" (2023) — arXiv:2312.08595 (preprint) — Geometric mean 4.7e15 FP4/J, roughly 200 times.
• "Enhancing Gate Control… in Amorphous Oxide TFTs" (2025) — arXiv:2506.14156 (preprint) — Protruding electrodes, targeting BEOL.
• "Time-Dependent Dielectric Breakdown… on nMOS FinFETs" (2024) — arXiv:2402.00886 (preprint) — Small area falls short of the 10-year specification.
• "Enhanced Circuit Densities in Epitaxially Defined FinFETs…" (2016) — arXiv:1604.04454 (preprint) — Footprint 2x, density may be equal or greater.
• "Contact resistances in trigate and FinFET devices…" (2016) — arXiv:1602.07545 (preprint) — Electrostatic control under the spacer is the main culprit.
• "Negative Capacitance Enables FinFET Scaling…" (2020) — arXiv:2007.14448 (preprint) — "3nm node" = IRDS 16 nm specification value.
• "SiGe Indentation Process Control…" (2022) — arXiv:2201.04725 (preprint) — Two branches of non-destructive in-line metrology.
• "3D Atomic-Scale Metrology… via Electron Ptychography" (2025) — arXiv:2507.07265 (preprint) — Prototype 5 nm channel, bulk atoms 60%.
• "Gate Electrostatic Controllability… in Nanotube GAAFET" (2023) — arXiv:2304.08175 (preprint) — 62% and 57% by changing shape alone.
• "The interface states in GAA transistors" (2023) — arXiv:2308.08101 (preprint) — Interface states are why nanosheets are preferred.
• "Gate-Drain Leakage Enhanced by… Barrier Lowering" (2026) — arXiv:2603.21015 (preprint) — A new leakage path in GAA.
• "Sub-5 nm GAA InP Nanowire Transistors…" (2023) — arXiv:2308.14045 (preprint) — 4 nm gate length satisfies ITRS.
• "Achieving short high-quality GAA structures…" (2018) — arXiv:1810.03359 (preprint) — SS 38 mV/dec at 77 K.
• "Towards sub-30nm Contacted Gate Pitch…" (2022) — arXiv:2203.06364 (preprint) — Gate pitch 10 nm margin.
• "CMOS-compatible Strain Engineering…" (2024) — arXiv:2405.09792 (preprint) — Median 60% and 45%, cause is simulation interpretation.
• "Ab-initio NEGF Perspective of Ultra-Scaled CMOS…" (2020) — arXiv:2010.06867 (preprint) — 12 nm → 6 nm → 1 nm.
• "Valley-Landscape Engineering in Bilayer WSe2…" (2026) — arXiv:2606.08955 (preprint) — SS fixed, only mobility tuned.
• "Chiplet Actuary: A Quantitative Cost Model…" (2022) — arXiv:2203.12268 (preprint) — Chiplet cost advantage and its conditions.
• "Security Assessment of Interposer-based Chiplets" (2020) — arXiv:2010.13155 (preprint) — Detecting Trojan horses with functionally distinct chiplets.
• "Challenges… via Heterogeneous Chiplets" (2023) — arXiv:2311.16417 (preprint) — Discussing benefits and remaining challenges together.
• "Chiplets on Wheels…" (2024) — arXiv:2406.00182 (preprint) — The silicon industry is the entity shifting.
• "Floorplet: Performance-aware Floorplan Framework…" (2023) — arXiv:2308.01672 (preprint) — Communication cost reduced by 24.81%.
• "Tiny Chiplets Enabled by Packaging Scaling…" (2025) — arXiv:2511.10760 (preprint) — Simplifying that circuit opens the path to miniaturization.
• "CMOS 2.0 — Redefining the Future of Scaling" (2025) — arXiv:2510.04535 (preprint) — From geometric scaling to heterogeneous 3D integration.
• "Stack up your chips: Betting on 3D integration…" (2020) — arXiv:2005.10866 (preprint) — Benefits vary by application and design (lecture).
• "Channel-last gate-all-around nanosheet oxide… transistors" (2025) — arXiv:2512.21330 (preprint) — 63 mV/dec without post-processing.
• "Recent Progresses… of UV Laser Annealing" (2022) — arXiv:2209.05337 (preprint) — Annealing that heats only the top layer.
• "Overview of Beyond-CMOS Devices and A Uniform…" (2013) — arXiv:1302.0244 (preprint) — Estimation methodology and comparison results.
• "Charge-Resistance Approach to Benchmarking…" (2013) — arXiv:1308.4748 (preprint) — New calculation method for energy-delay product.
• "Beyond-CMOS Device Benchmarking for Boolean and Non-Boolean…" (2017) — arXiv:1711.04295 (preprint) — Potential to surpass in non-Boolean.
• "Post-CMOS Compatible AlScN/2D Ferroelectric FET" (2020) — arXiv:2010.12062 (preprint) — PZT stalls at 130 nm.
• "TEXEL: A neuromorphic processor…" (2024) — arXiv:2410.15854 (preprint) — Test platform combining new devices and CMOS.
• "Breakdown of Ohm's Law by Disorders…" (2026) — arXiv:2601.01283 (preprint) — Linear scaling breakdown and model.
• "Is there a Moore's law for quantum computing?" (2023) — arXiv:2303.15547 (preprint) — Qubit metrics do not improve together.