Nothing In Between — How Bonding Two Surfaces Directly Became the Center of the Process

60 Seconds of Argon Ion Beams

In 2003, two copper films bonded directly to each other at room temperature. The copper films were coated onto a wafer—a thin, round silicon plate used to make chips ("Lithography — Painting Circuits with a Brush of Light")—measuring 8 inches, with a film thickness of 80 nanometers. Only one thing was done before joining them: they were exposed for 60 seconds to a low-energy argon ion beam of 40 to 100 electron volts in an ultra-high vacuum with almost all the air removed, stripping away carbon contaminants and the thin oxide film that naturally formed on the copper surface. Then, when the two sheets were brought together, they stuck. There was no need to heat them. The bond was already strong enough at room temperature that when pulled apart, the strength rivaled that of bulk copper. Looking at the cross section through a transmission electron microscope, there was neither an intermediate layer nor a gap at the contacting surface (DOI: 10.1116/1.1537716, measured).

If you make the surface this clean inside an ultra-high vacuum, two copper faces stick even at room temperature. The difficult part was pulling that off inside a semiconductor fab. It had to be done repeatedly, aligned to the nanometer scale, and attached across the entire surface of a 300-millimeter diameter wafer. This article follows those 20 years.

The papers cited in this article fall into two tiers. One consists of process papers that actually spun wafers and measured things. Numbers like how many nanometers the surface roughness is, what interval the contact points are spaced at, or at what temperature they bonded come from here. The other consists of papers run through calculations. These simulated the bonding process, modeled yield, or rearranged chips using design tools. Yield is the proportion of manufactured items that come out in a state that can actually be sold, and "They Chose Not to Make It One Chip — The Bill for Cutting It Apart" covers this term in detail. These two tiers are not values measured with the same ruler. Therefore, at every point where the weight is heavy, whether it is a measurement, simulation, model, specification value, review, survey, or background statement is noted in parentheses. This label is attached to the sentence, not the paper. The same paper may be a measurement in one place and a background statement in another.

Things Placed Between Them

To stack chips vertically, a specific point on the lower chip must be electrically connected to a specific point on the upper chip. For a long time, that job was handled by an object wedged between two surfaces.

A microbump is a tiny metal pillar with solder on its ends, wedged between two surfaces to connect chips. Short pillars are set densely between the upper and lower floors, and the solder on the ends of the pillars is heated and pressed to stick them together. This method of applying heat and pressure together to bond them is called thermocompression bonding. The empty space left between the pillars is filled by flowing in resin.

Even as of 2019, stacked chip bundles formed layers using this method. HBM, memory placed right next to a computing chip and used alongside it, is an example. The stacked chips are connected vertically by through-silicon vias—vertical holes pierced right through the chips from top to bottom, filled with a conductive metal like copper (“Fetching Is Slower Than Computing — The Memory Bottleneck and HBM”). The contact points between layers are made by bonding solder-coated microbumps with thermocompression. This process has low throughput and cannot go below a 40-micrometer pitch (DOI: 10.1109/ectc.2019.00100, background statement). This means it was difficult to place the pillars any denser in the memory stacking process covered by that paper.

The inability to shrink the pillars was not the only problem. As of 2017, three additional problems were noted. The assembly was complex and expensive, so it was not widely used. When the solder solidifies, it forms a hard but brittle intermetallic compound layer, and this layer reduces the current's ability to withstand long durations. The resin filling the space between the chips nearly doubles the stacked height and heavily blocks the path for heat to escape. The number of layers that could be stacked around that time was four on top of the base chip (DOI: 10.1109/ectc.2017.341, background statement).

A Scale Called Spacing

There is one scale that follows us throughout this story.

The junction spacing is the distance from the center of one connection point connecting chip to chip to the center of the very next connection point. Think of it like theater seats: not the width of the chair itself, but the distance from one backrest to the next. This value ultimately determines how many people can sit in the same area.

Cut the spacing in half, and the number of connection points that fit into the same area becomes four times greater. As the connection points get denser, the two chips are linked by tens of thousands of thin pathways instead of a few thick ones. It is a direction of increasing the number of pathways rather than making a single pathway fast. Therefore, this single value determines the number of signals that can travel back and forth between the two chips, and the number of signals determines the structure that can be placed on top of it. A 2023 reliability review concluded that through-silicon vias and the method of bonding two entire wafers face-to-face together hold the key to reaching a connection density exceeding 1 million per square millimeter (DOI: 10.1109/tdmr.2023.3327664, review).

When You Face Two Surfaces Straight Against Each Other

Hybrid bonding is a joining method where the surfaces of two chips are smoothed and faced against each other, sticking metals to metals and insulating films to insulating films directly all at once. Neither solder nor adhesive is placed in between. An insulating film is a thin membrane that electricity cannot pass through, and copper contact points are embedded within that film, exposed at the surface. Much like how two very clean sheets of glass cling together on their own when layered, the insulating film side sticks first, and the metal side must be heated afterward to stick.

Those two stages look like this. When the chip is placed upon the counterpart surface, the insulating films cling together with a weak force. Then, when the whole thing is heated, that weak bond changes into a chemical bond, and the copper embedded within the insulating films permeates across the contacting face to merge with each other, creating a path through which electricity flows (DOI: 10.1109/ectc51687.2025.00011, 2025, process development and definition statement).

Post-bonding heat treatment is a process where two surfaces are faced and stuck together and then heated as a whole, making atoms permeate across the contacting face to merge with each other. If you press two blocks of cold clay together they merely pretend to stick, but when you heat them the boundary blurs and they become a single mass.

The name "hybrid" comes from here. This is because when two faces with copper and insulating film exposed side by side are faced against each other, metal bonding and insulating film bonding occur simultaneously. In 2016, as a result of joining 300-millimeter wafers using this method at 3.6-micrometer and 1.8-micrometer intervals, when the surface was well activated and the insulating film was made extremely smooth, they stuck together seamlessly at room temperature. A strong bond was achieved with a heat treatment at a low temperature of just 250 degrees (DOI: 10.1109/ectc.2016.205, measured).

For this method to stick properly, four things must be met. The surfaces must be flat, they must be clean, the positions must match, and they must bond at a temperature low enough for the underlying layer to withstand. The following four sections will follow one by one.

Polishing the Surface to Atomic Scale

The price for eliminating solder is billed immediately. Because solder melts and flows, it fills in gaps on its own even if the surface is a bit bumpy. Direct bonding has no such margin. The two facing surfaces must be flat from the beginning.

Chemical mechanical planarization is a planarization process that pours a chemical-mixed polishing slurry onto the wafer surface and rubs it with a pad, mechanically shaving away the chemically softened layer. Following its English abbreviation, it is commonly called CMP. It resembles sanding wood with wet sandpaper, except that instead of water, it uses chemicals that make the surface slightly soft. That is why it becomes much flatter than when grinding with force alone.

The polished surface is evaluated by four properties: the degree to which the polished copper is dished out like a bowl, the degree to which the insulating film is scraped away together, the roughness of the insulating film surface, and the degree of height variation when moving from a dense copper area to a sparse area. Final polishing is usually divided into two stages. A 2023 study measured dishing and edge roll-off with an atomic force microscope, which traces heights with a needle, while narrowing the spacing from 5 micrometers down to 1 micrometer (DOI: 10.1109/ectc51909.2023.00138, measurement).

Looking at the numbers gives a sense of how flat it is. There are results where the arithmetic mean roughness was reduced to 0.3 nanometers and dishing to 1 nanometer in copper made into a nano-sized nanotwin structure through two-stage polishing. A nanotwin structure is a structure where very thin layers with crystal orientations reversed like a mirror are stacked layer upon layer. Two wafers were bonded at 200 degrees Celsius using that surface, passed a thermal cycle test repeating heat and cold, and the tensile strength exceeded 10 megapascals. However, the authors noted that that low bonding temperature critically relies on the aligned copper and the seamless bonding interface. Polishing alone did not lower the temperature (DOI: 10.1109/ectc32696.2021.00068, 2021, measurement).

Dishing is not always a defect that must be eliminated. There is a polishing process that intentionally makes the copper of the upper wafer protrude slightly and the copper of the lower wafer recede slightly. This process also intentionally made the sizes of the upper and lower pads different. This is because the size difference serves as margin to absorb misalignment. By doing so, it was shown that attaching a 360-nanometer upper pad to a 720-nanometer lower pad at a 1.44-micrometer pitch works, and attaching a 180-nanometer pad to a 540-nanometer pad at a 0.72-micrometer pitch works as well (DOI: 10.1109/iedm.2017.8268486, 2017, measurement). The goal of flatness is closer to deciding what shape the surfaces will take when they meet than to eliminating height variations.

Even a Tiny Amount of Contamination Kills a Device

Being flat is not enough. It must be clean.

When copper pads sized 0.4 micrometers to 0.7 micrometers are bonded wafer-to-wafer, two problems arise. One is that as the pads become smaller, copper diffuses into the insulating film. The other, unexpectedly, comes from the cleaning process. The plasma process used to clean the surface bounces copper back out, contaminating the interior of the equipment, and that tiny amount electrically shorts and kills the device (DOI: 10.1109/ectc51909.2023.00238).

That study first proposed optimal nitrogen plasma conditions using reactive molecular dynamics calculations that track the movement of individual atoms on a computer (simulation). Under those conditions, the bonding energy between insulating films is reported to be above 2.0 joules per square meter, and the copper oxide layer below 2 nanometers. The abstract does not clarify whether these two values came from calculations or from fabrication and measurement. It was confirmed through acoustic and electron microscope analysis that the interface bonded under those conditions was gapless, well-mixed, and properly aligned (measurement). The authors concluded that this condition meets the contamination-free standard. Because it does not contaminate the equipment even when run continuously, it is a better surface activation method (DOI: 10.1109/ectc51909.2023.00238, 2023, simulation + measurement). Even within a single paper, values determined by calculation and values obtained by fabrication and measurement cannot be read with the same weight.

A Ruler to Measure Misalignment

The third requirement is aligning the positions.

Overlay error is the measured value of how much two layers pasted and stacked on top of each other are actually misaligned at the points where they should touch. It is like punching holes in two pieces of paper, overlapping them, and measuring how many millimeters apart the centers of the holes are shifted. The smaller the holes, the more fatal the same misalignment becomes.

The values below are arranged in chronological order. They should not be read as an evolution curve for a single equipment maker or a single company. The wafers, structures, measurement methods, and number of measurement points all vary from paper to paper.

In 2010, the alignment after facing and bonding 300-millimeter wafers was tuned to below 500 nanometers, and in condition-optimized samples, it dropped to roughly 190 nanometers. At the interface of a structure connecting short passages vertically—that is, vias 1 micrometer to 5 micrometers in diameter—linked like a chain, there were no gaps, and traces of copper diffusing into each other were confirmed under a microscope (DOI: 10.1109/3dic.2010.5751447, measured).

In 2015, less than 200 nanometers was reported across the entire surface of a 300-millimeter wafer (DOI: 10.1109/eptc.2015.7412403, measured).

Yet a 2016 conference paper described the background like this. As of 2016, the best wafer-to-wafer alignment error was around 400 nanometers, and development was underway to reduce that to 200 nanometers (DOI: 10.1109/3dic.2016.7970002, background statement). This is worse than the value in the previous paragraph. The 2010 paper noted roughly 190 nanometers as the highest accuracy up to that point, whereas the 2016 paper noted the best value as around 400 nanometers. The abstract does not explain the difference, but what is different is visible. The 2015 value was measured across the entire 300-millimeter surface for a specific sample topped with copper pads for an image sensor. The 2016 sentence is a description of the state of its field written the following year by a different paper dealing with three-dimensional wiring in general. Even for values with the same name, if the sample, the time, or who measured it differs, they cannot be directly compared.

In 2023, approximately 50 nanometers was reported by continuously bonding 12 sets of wafers. At 95 percent of the measurement points, the misalignment was 40 nanometers or less, and at 80 percent, it was under roughly 30 nanometers. The same paper noted that correction works even on a wafer warped like a saddle by ±250 micrometers, and that if reproducibility is raised further, there is a high likelihood it can reach 25 nanometers or below. The latter two are values obtained through analysis, not measured values. The authors concluded that this result shows the possibility of further reducing the wafer-to-wafer bonding gap (DOI: 10.1109/ectc51909.2023.00283, measured + analytical).

A 2022 paper from the same research line has one more qualifier. When actual device-bearing wafers were bonded using the equipment that achieved 50 nanometers on test wafers, it was 59 nanometers. This is because actual device wafers are more vulnerable to distortions that occur during bonding. The test wafer side, which yielded 50 nanometers, was measured at 397 points within a 142-millimeter radius per wafer (DOI: 10.1109/eptc56328.2022.10013152, measured). There is a gap between the test wafer's top record and the production wafer's value.

Misalignment Occurs the Moment They Bond

The reason alignment is difficult lies in two steps. Precisely overlapping two wafers is one step, and keeping them in place after they have bonded is another.

The difference between the two steps is revealed in the numbers. The alignment capability of a single tool itself was under 100 nanometers, but the accuracy measured after actually bonding 300-millimeter copper wafers was 260 nanometers (DOI: 10.1109/3dic.2015.7334575, 2015, measured data). This means that the accuracy achievable during overlap and the accuracy after bonding were not the same. The authors noted that analyzing those errors by component to find the causes is useful.

A bonding wave is a motion where two wafers start sticking at a single point and that contact spreads outward like a wave. Two wafers do not bond across their entire surface at once. While alignment precision in positioning the two wafers plays a large role in post-bonding alignment error, where this wave starts and how it spreads is just as crucial. Residual stress and warping remaining in the wafer alter the movement of the wave, and stress soon manifests as pattern distortion and additional misalignment. A 2015 conference paper addressing this issue concluded that although typical distortion values are already well below 50 nanometers, further optimizing both wafer bonding and wafer preparation/pretreatment remains the key (DOI: 10.1109/ectc.2015.7159701, process discussion).

Surface chemistry also interferes with this wave. The results vary depending on whether the insulating film surface is treated with nitrogen plasma or oxygen plasma. The speed at which the wave spreads hardly changed even when the conditions were altered. However, the amount by which the wafer shifted in the in-plane direction after bonding was markedly greater on the nitrogen side. Conversely, the bonding strength was highest when the nitrogen plasma was applied at 100 watts. Oxygen plasma made the surface act more like a uniform oxide film, resulting in less shifting and a more stable position, but lower strength. The conclusion of the authors who measured this in 2026 is that there is a trade-off rooted in surface chemistry between strength and alignment (DOI: 10.1021/acsaelm.6c00446, measured data).

In this study, using nitrogen plasma to make the bond stronger caused the position to shift more, and using oxygen plasma to preserve the position resulted in a bond less strong than the optimal nitrogen condition. This pair demonstrates that bonding strength and positional alignment do not operate independently.

The Race to Lower the Bonding Temperature

The fourth requirement is temperature. When you stack in three dimensions, devices like transistors already built at the bottom receive the heat from the upper-layer processes together. Some devices cannot withstand that heat. Therefore, each process has a limit to the heat it can endure—in other words, a thermal budget—and the bonding temperature must fall within it.

The temperatures below are values obtained by different papers through different materials, structures, and tests. They should not be read as points connected on a single curve.

The process of bonding copper and oxide typically required around 400 degrees back then, and that temperature was undesirable for heat-sensitive chips. The result of bonding both copper-to-copper and oxide-to-oxide at 200 degrees through a two-step activation process involving sequential plasma and acid treatments came from that background (DOI: 10.1109/icept52650.2021.9568007, 2021, measured data).

One key to lowering the temperature was the shape of the copper grains. A 2022 study attached 8-millimeter-by-12-millimeter dies to a 300-millimeter wafer. A die is a single piece of a chip cut from a wafer. About 35,000 pads with a diameter of 10 micrometers were connected at intervals of 40 micrometers. This is the same number as the 40 micrometers where we mentioned microbumps could not go any lower earlier, but here it is the interval of a test structure chosen to observe the thermal budget. Copper was made in three types—conventional wiring, nano-sized twin structure, and fine grain—and compared while heat-treated from 150 degrees to 270 degrees. As a result, solid metal bonds were formed even at a low temperature of 180 degrees. The notion that the final heat-treatment temperature can be lowered by 20 to 40 degrees solely through differences in microstructure is what the authors wrote that their results suggest. It is not a nailed-down conclusion (DOI: 10.1109/ectc51906.2022.00036, measured data).

Polishing methods also affect temperature and time. Direct copper-to-copper bonding has typically been done above 300 degrees, and that temperature is harmful to devices. Therefore, nano-twin copper films aligned in the (111) direction were polished using chemical mechanical planarization and electropolishing, which smooths the surface by melting it with electricity, respectively, and compared by bonding at 150 degrees. In a comparison within the same paper, the bonding quality of the chemical mechanical planarization side was better. That film had an extremely smooth surface and virtually no pre-existing gaps at the interface, which made it possible to reduce the time required for bonding down to 10 minutes (DOI: 10.3390/ma15030937, 2022, measured data).

As a method of preventing oxidation by covering the copper surface with gold, fine-pitch bonding at 120 degrees has been reported (DOI: 10.1109/jeds.2021.3114648, 2021, measured data).

This is as far as the four requirements go. The surface must be flat on an atomic scale, clean without even the tiniest amount of contamination, its position must be maintained while bonding, and it must bond at a temperature low enough for the lower layer to withstand. And as seen in the comparison between nitrogen and oxygen plasma, bonding strength and alignment can be traded off against each other.

So What Has Improved?

Papers reporting what was gained in return for this usually did not build chips by spinning wafers, but rearranged chips using design tools. All of the gain figures below are the results of calculation using design and analysis tools. Only one study at the end of this section actually made a test structure, and even that did not measure gains, but looked together at how process variation affects resistance and capacitance using measurements and simulation models.

A 2022 journal paper designed industrial-scale three-dimensional processors in two different ways. One connects with microbumps, and the other attaches directly. After completing the physical design including the power delivery network across multiple process generations and multiple bonding pitches, a comparison showed that the tight-pitch direct bonding side outperformed the microbump side by up to 76 percent in performance or reduced voltage drop by 17 millivolts (DOI: 10.1109/tcpmt.2022.3221025, design experiment). Voltage drop is when electricity loses power while flowing along a line with resistance, arriving at a lower voltage than when it started, which is covered in detail in "Turn the Power Around and the Heat Gets Trapped — The Bill for Grinding Away the Silicon Under the Transistors". This value is compared among control groups established within the same design flow. It is not a comparison made by stitching together values from different papers.

That paper even offered a prescription to fix the losing side. After the authors determined that sharing metal between layers is crucial for both signals and power, they proposed a method to share capacitors made by overlapping metal and insulators, reducing the instantaneous voltage drop of the microbump side by up to 77 millivolts (DOI: 10.1109/tcpmt.2022.3221025, design experiment).

A 2019 conference paper extended commercial design tools to create a flow connecting two layers with copper pads spaced around 1 micrometer apart. Using that flow, a single processor core was split into a memory layer and a logic layer, then placed and routed inside the design tool. The results compared with designing the same circuit in a two-dimensional plane were a maximum 40 percent reduction in total wire length, a 25 percent reduction in the longest wire, and a 19 percent improvement in critical path timing (DOI: 10.1109/3dic48104.2019.9058901, design experiment). The 76 percent in the previous paragraph is compared to microbumps, and these three are compared to two-dimensional design. Because the comparison targets are different, the two values cannot be placed on the same line.

The heat also changes. The 2017 paper noted earlier where the resin blocks the heat path used a thermal analysis tool to simulate the temperatures of a memory stack built with microbumps and a stack attached directly copper-to-copper, under the same ambient temperature and the same power per die. The junction temperature difference was 9 degrees, and in the eight-layer configuration, the junction temperature on the direct bonding side was 25 percent lower. The electrical side was also better. The insertion loss—the degree to which signals weaken as they pass in high gigahertz bands ("If the Board Warps, Nothing Above It Helps — The Bill for a Glass Base and In-Package Light")—and crosstalk where signals from neighboring lines mix in were smaller, and the parasitic capacitance that unintentionally arises and makes signals sluggish was 30 percent of that of the microbump bond (DOI: 10.1109/ectc.2017.341, simulation). This value was obtained using thermal and electromagnetic analysis tools, so it is not measured with the same ruler as the values from the preceding two papers obtained by placing chips with design tools.

There is also a side that actually fabricated and measured it. This is a study that built a three-dimensional test structure with bonding pitches lowered from 6.8 micrometers down to 1.44 micrometers, and observed how resistance and capacitance respond to process variation. The factor that commonly affects both resistance and capacitance was the alignment error of the upper and lower wafers (DOI: 10.1109/eptc50525.2020.9315028, 2020 year, measurement + simulation model). Aligning positions does not just determine whether they stick or not. It also determines the electrical properties after they are stuck.

Where It Is Already Used

The papers that cite this technology as already integrated into products point not to processors, but to camera image sensors and 3D NAND memory. Conference papers from 2019 and 2023 mention both side by side, and the 2023 paper notes that the pitch is wider than 1 micrometer (DOI: 10.23919/iwlpc.2019.8913862; DOI: 10.1109/ectc51909.2023.00010, background statement). The studies below are demonstrations from that application side.

A 2014 Electrochemical Society presentation paper is an early demonstration targeting image sensors. The authors considered that through-silicon vias exceeding 5 micrometers in diameter are unsuitable for local wiring connecting nearby points within a chip. Therefore, they embedded gold electrodes on an insulating film, activated the polished surfaces with argon and oxygen plasma, and pressed them together at 200 degrees Celsius for 60 minutes with 2,000 newtons of force. The average roughness of the oxide surface was 0.15 nanometers, the smallest gold electrode diameter was 3 micrometers, and no gaps were visible at the interface. On the two layers bonded in this way, they placed transistors—tiny switches turned on and off by electricity ("A Transistor Is a Switch — A Tiny Faucet You Open and Close with Electricity")—separated into n-type and p-type. When they used these to build a 3D inverter, the simplest circuit that flips and outputs an input, its performance showed no difference from planar chips made at the same period. A 101-stage ring oscillator, formed by connecting inverters in a loop to make them oscillate on their own, oscillated at 700 kilohertz at 1.8 volts. The authors cited the reduced circuit area, along with the fact that two types of transistors can be optimized separately on different wafers, as advantages (DOI: 10.1149/ma2014-01/37/1412, measured data).

It was soon confirmed that copper is not required. A method was developed to bond titanium and an oxide film for a 200-millimeter non-copper process using aluminum wiring, and the titanium pads were shrunk down to 3 micrometers square. The contact resistance of that 3D wiring was under 1 ohm, and the parasitic capacitance was under 2 femtofarads (DOI: 10.1109/ectc32862.2020.00044, 2020, measured data).

Evidence that shrinking the pitch does not weaken the structure also came from image sensors. Backside-illuminated image sensors, which receive light on the back surface without circuitry, were fabricated with pitches scaled down from 8.8 micrometers to 1.44 micrometers. Neither thermal cycling tests nor electromigration tests, which observe the phenomenon where prolonged current flow pushes metal atoms away, showed defects caused by the shrinkage of the pads (DOI: 10.1109/iedm.2018.8614570, 2018, measured data).

A different reason is discussed for memory. NAND flash is storage memory that retains its contents even when the power is turned off. A 2019 conference paper pointed out that some NAND flash structures require high-temperature memory processes and low-temperature logic processes to be handled together within a single wafer, ultimately resulting in a product that compromises on both thermal budgets. The idea is that if the two are made separately on different wafers, they can be optimized individually within their respective thermal budgets and then bonded (DOI: 10.23919/iwlpc.2019.8913862). The test structure in the same paper packed 115,000 connections at a 4-micrometer pitch into 3.61 square millimeters, achieving a minimum electrical yield of over 98 percent across all wafers. A similar yield was obtained in a longer chain connecting 500,000 pads with a 3-micrometer diameter spaced at a 10-micrometer pitch (DOI: 10.23919/iwlpc.2019.8913862, measured data). The notion that memory and logic could be built separately within different thermal budgets, echoing the earlier image sensor study where two types of transistors were optimized separately, is written in this paper as an expectation. The 98 percent yield is a value from a connection chain test structure, not from a device implementing that concept.

Whole Wafer or Die

Here a fork in the road appears. You can bond two wafers whole, or you can cut the wafer into chip pieces and mount them one by one onto another wafer.

Generally, bonding them whole aligns the positions more precisely, while bonding them in pieces makes it possible to mix chips of different sizes or pick and choose only good pieces filtered in advance. A 2024 review also noted that stacking chiplets in various shapes commonly requires the piece-by-piece approach (DOI: 10.1115/1.4064750, review).

The problem with the piece-by-piece approach arises the moment you cut. Dicing the wafer into pieces and handling those pieces itself contaminates the surface and complicates the process flow (DOI: 10.1109/ectc32696.2021.00018). That 2021 study selected a method that generates fewer particles during dicing and used a protective film covering the surface while cutting. It used a commercial flip-chip bonder that flips the chip and mounts it onto a substrate, and the alignment accuracy specification of that equipment was ±3 micrometers at the 3-sigma level. This criterion means that almost all cases fall within that range. The authors wrote that by tweaking the bonding process flow slightly, they could achieve very good alignment accuracy. The process variables were determined in advance through simulation results (DOI: 10.1109/ectc32696.2021.00018, measurements + simulation + equipment specification value).

This ±3 micrometers cannot be placed side by side with the 50 nanometers of the previous section. One is a specification value written in a commercial equipment manual and the other is a value measured by bonding wafers with dedicated bonding equipment, and their targets and conditions are also different.

Good results come out from the piece-by-piece side as well. By attaching pieces to a wafer with a 4-micrometer pitch and 2-micrometer pads, more than 98 percent electrical connectivity was confirmed across all 210 chains on the chip, and they passed thermal cycling, humidity, and high-temperature storage tests alike (DOI: 10.1109/ectc51909.2023.00178, 2023, measurements).

Time is also an enemy on the piece-by-piece side. Because pieces have their cut side surfaces exposed more to wet processes and face longer waiting times, the problem of moisture seeping into the interface is expected to become more severe. Moisture weakens bonds, creates voids, and raises the resistance of copper pads. That 2025 study introduced a process for bonding thin pieces with a thickness of 50 micrometers, passing a test of withstanding 168 hours at 85 degrees Celsius and 85 percent humidity as well as a 1,000-cycle thermal shock test alternating between minus 40 degrees and 125 degrees Celsius (DOI: 10.1109/ectc51687.2025.00011, measurements).

There are also attempts to calculate through math which of the two is better. By putting misalignment, particle defects, copper dishing variations, surface roughness, and copper pad density into a single framework, a model and public simulator that calculate the yields of the whole-wafer bonding side and the piece-by-piece side together have been released (arXiv:2511.05506, 2025, model/simulation, preprint). The number of over 1,000 times reported by the authors is the reduction in computation time. It must not be read as a difference in yield. It means that the approximate analytical model achieved the same accuracy as the simulation while being that much faster.

What They Have Taken On Anew

Hybrid bonding is also structured as the one that failure analysis practitioners name as the hardest to analyze. In an industry survey (preprint) published in 2026, about 100 anonymous responses were gathered from various organizations spanning semiconductor design, packaging, systems, and failure analysis, and the response naming hybrid bonding as the new structure most difficult to analyze ranked first at 54 percent. 69 percent of the respondents were dealing with heterogeneous integration and chiplet products or 3D products that put pieces of different properties and processes into a single package. As the most important acceleration factor going forward, higher-resolution imaging techniques to peer inside chips without breaking them were chosen with 8.18 points out of 10, and 83 percent supported a data standardization system (arXiv:2606.22149, survey). These numbers show the state of affairs seen by about 100 anonymous responses at the point of 2026.

The survey abstract did not write down the reasons separately, but it gave as background that failure analysis has come to deal with package structures buried ever deeper. The bonding interface between two chips is precisely such a spot. What a 2023 reliability review pointed out at that interface includes the intensity of polishing, copper migrating along the interface, and the effect that bonding voids have on the electromigration performance of the copper pads. This review showed that it is important to make the polishing gentle. This is because grinding hard damages the insulating film, and the damaged insulating film soon becomes a defect (DOI: 10.1109/tdmr.2023.3327664, review).

If the spacing is reduced further, there is also a point where the material itself cannot endure. A 2023 study that examined design layout, insulating film types, copper polishing depth control, and alignment control together targeting spacing under 0.5 micrometers (500 nanometers) noted in the final sentence of its abstract that it also investigated starting from what density of packed copper this material system begins to break down (DOI: 10.1109/ectc51909.2023.00010, measurement). Another device conference paper from the same year put a spacing of 0.4 micrometers (400 nanometers) in its title. This figure is only in the title and not in the main text of the abstract. That paper solved the alignment problem with a test design placing circular pads on a hexagonal lattice, and analyzed the relationship between alignment error and contact resistance, yield, and reliability (DOI: 10.1109/iedm45741.2023.10413829, measurement).

There is also the problem that standards do not exist. Because insulating film materials vary wildly, it is difficult to mix and bond wafers made in different fabs. As a result of pairing four insulating films and measuring and comparing even the bonding energy and the micro-void density of the interface, the combination of a nitride film without hydrogen and an oxide film with hydrogen produced the highest bonding energy among the combinations that study examined, and showed no voids after a 250-degree heat treatment. The authors proposed this combination as a candidate for a standard (DOI: 10.1109/ectc51529.2024.00100, 2024, measurement). A 2024 review pointed to the same place. To handle pieces coming from different process generations and different fabs, equipment development and industrial standards must be built together (DOI: 10.1115/1.4064750, review).

Attaching Has Become Central

What has changed is not just the gap between contact points.

In the method using microbumps, attaching was an assembly step that came after the devices were fully made. In hybrid bonding, how smoothly the surface is polished down to a few nanometers, which gas is used to activate it, and how the meeting wave is controlled determine the device's resistance, yield, and lifetime. One study showed that the trade-off where gaining strength means losing alignment is rooted in surface chemistry (DOI: 10.1021/acsaelm.6c00446, measured), that polishing too hard degrades reliability (DOI: 10.1109/tdmr.2023.3327664, review), and that the copper design density at which the material system starts to break down has become a subject of process research (DOI: 10.1109/ectc51909.2023.00010, measured). These sentences are not sentences of assembly processes, but of device processes.

The method of pressing with heat and pressure also keeps its place. However, it is not a solder-coated pillar, but thermocompression bonding where copper pieces are pressed together without solder. A 2023 conference paper divided this method into two stages, achieving a throughput of over 300 per hour while meeting a pitch of 10 micrometers or less. The force required to shear a single 2-millimeter-square die sideways averaged over 110 Newtons, and the contact resistivity between the coppers was comparable to the lowest values reported in hybrid bonding. And the authors concluded as follows: for uses such as 3D stacking and interposers down to a pitch of about 7 micrometers, thermocompression bonding is a better choice simply because it is simpler than hybrid bonding (DOI: 10.1109/ectc51909.2023.00067, measured). An interposer is a thin plate with multiple chips placed side by side and only dense wiring laid out to connect between them ("The Bottleneck Was Never Compute — Ten Years of Stacking Memory Beside the Processor"). However, the 10 micrometers and 7 micrometers in this paper are values written as bump pitches in the abstract, and the 0.5 and 0.4 micrometers right below are bonding pad pitches. They are rulers measuring different things, so they cannot be lined up in a single row.

The limit of the tighter side has not been decided yet either. A 2024 review summarizing the literature noted that the feasibility of pitches under 0.5 micrometers has already been shown in wafer-to-wafer bonding methods. However, it immediately followed by writing that the limit of expansion going down below 0.4 micrometers is still being explored. The problem of handling pieces and the problem of mixing chips from different factories were also left open (DOI: 10.1115/1.4064750, review). This sentence is not a value measured by the paper itself, but a statement summarizing the literature.

In that 2003 experiment, the preparation it took for two copper films to bond at room temperature was a single 60-second ion beam. It took 20 years after that to repeat the same thing across an entire 300-millimeter wafer, with nanometer positional accuracy, and at a temperature that does not damage the underlying devices.

Direct bonding has not taken over every spot. By removing what used to be wedged in between, the act of attaching itself became the act of making the device. From that moment on, performance began to be determined not only by how small you draw the transistors, but also by how flat, clean, and accurately you face the two sides together. Which method to use at which pitch still varies from paper to paper, and that split shows where this field stands.

Source Papers

• "Room-Temperature Surface-Activated Direct Bonding of Copper" (2003) — DOI: 10.1116/1.1537716 — 60-second argon ion beam, bulk copper-grade strength and gap-free interface without heat treatment.
• "Low-Temperature Copper Interconnection for Chip-to-Wafer Hybrid Bonding" (2019) — DOI: 10.1109/ectc.2019.00100 — Microbumps cannot go below 40 μm (background), room-temperature bonding + 150–300 ℃ heat treatment.
• "Thermal and Electrical Performance of Direct-Bonded Interconnects for 2.5D and 3D ICs" (2017) — DOI: 10.1109/ectc.2017.341 — Brittle compounds and resin nearly double the height (background), simulations show 9-degree junction temperature difference and 30% parasitic capacitance.
• "Reliability Challenges of TSV and SiCN Wafer Bonding" (2023) — DOI: 10.1109/tdmr.2023.3327664 — The key to densities over 10⁶ per 1 mm², smooth polishing, copper migration, and bonding voids.
• "Thin Die Bonding Process for Yield and Reliability" (2025) — DOI: 10.1109/ectc51687.2025.00011 — Defines a two-stage process of room-temperature weak bonding → heat treatment → copper diffusion, addressing die moisture absorption with a 50 μm thickness process.
• "Ultra-Fine Pitch Face-to-Face Wafer Bonding Combined with Via-Middle TSV" (2016) — DOI: 10.1109/ectc.2016.205 — The basis for naming it 'hybrid', 3.6 and 1.8 μm pitches on 300 mm and 250 ℃ heat treatment.
• "Impact of Dielectric and Copper Via Design on Wafer Bonding" (2023) — DOI: 10.1109/ectc51909.2023.00138 — Four post-polishing surface properties (dishing, erosion, roughness, and density-dependent height variations), tracing 5 to 1 μm.
• "Low-Temperature Wafer Hybrid Bonding Using Nanotwin-Structured Copper" (2021) — DOI: 10.1109/ectc32696.2021.00068 — Roughness of 0.3 nm and dishing of 1 nm in nanotwin copper, bonded at 200 ℃. Low-temperature relies on oriented copper and continuous interfaces.
• "Sub-2 μm Pitch Cu/SiCN Wafer Bonding" (2017) — DOI: 10.1109/iedm.2017.8268486 — Protrusions on top and depressions on bottom, securing alignment margin by varying pad sizes. 1.44 μm and 0.72 μm.
• "Contamination-Free Cu/SiCN Bonding Process for Devices with Sub-1 μm Pitch" (2023) — DOI: 10.1109/ectc51909.2023.00238 — Proposes nitrogen plasma conditions via molecular dynamics (2.0 J/m² and 2 nm layer hierarchy unconfirmed), gap-free and contamination-free status confirmed by analysis.
• "Post-Bonding Alignment Better Than 500 nm in 300 mm Face-to-Face Wafer Bonding" (2010) — DOI: 10.1109/3dic.2010.5751447 — Around 190 nm under optimal conditions, no gaps at the via chain interface.
• "200 nm Alignment Accuracy in Wafer Bonding for Image Sensors" (2015) — DOI: 10.1109/eptc.2015.7412403 — Demonstrated under 200 nm across a 300 mm full wafer.
• "Importance of Alignment Control in Permanent Bonding" (2016) — DOI: 10.1109/3dic.2016.7970002 — Outlook that a pitch of 5 μm or less is needed, with the best alignment error at the time around 400 nm (background).
• "50 nm Bonding Alignment Error Achieved by High-Precision Alignment Technology" (2023) — DOI: 10.1109/ectc51909.2023.00283 — About 50 nm across 12 consecutive sets (values below 25 nm are analytical rather than measured), concluding with the possibility of further pitch reduction.
• "50 nm Bonding Alignment Error Demonstration and Improvement Study" (2022) — DOI: 10.1109/eptc56328.2022.10013152 — 59 nm on actual device wafers, with 397 measurement points per wafer.
• "Novel Precision Wafer Bonding Technology for 3DICs" (2015) — DOI: 10.1109/3dic.2015.7334575 — Alignment capability is under 100 nm, but post-bonding accuracy is 260 nm.
• "Influencing Factors of High-Precision Fusion Bonding for Monolithic Integration" (2015) — DOI: 10.1109/ectc.2015.7159701 — Post-bonding alignment is determined by the initiation and control of the bonding wave. Distortion is below 50 nm, but concludes that further optimization is the key.
• "Bonding Wave and Distortion in Plasma-Activated SiCN Direct Bonding" (2026) — DOI: 10.1021/acsaelm.6c00446 — Nitrogen increases strength and shifts, while oxygen does the opposite. The trade-off between strength and alignment.
• "Low-Temperature Cu/SiO₂ Bonding Using Two-Step Cooperative Surface Activation" (2021) — DOI: 10.1109/icept52650.2021.9568007 — Lowers the conventional ~400 ℃ (background) to 200 ℃, bonding copper-to-copper and oxide-to-oxide alike.
• "Effect of Copper Microstructure on Bonding Thermal Budget" (2022) — DOI: 10.1109/ectc51906.2022.00036 — Compares three microstructures at 150–270 ℃, achieving bonding at 180 ℃. A 20–40 degree reduction is "suggested by the results".
• "Interface Analysis of Low-Temperature Direct Bonding of Polished Nanotwin Copper Films" (2022) — DOI: 10.3390/ma15030937 — In-paper comparison favors chemical mechanical polishing, at 150 ℃ for 10 minutes.
• "Low-Temperature Fine-Pitch Cu/SiO₂ Bonding Using Gold Passivation" (2021) — DOI: 10.1109/jeds.2021.3114648 — Covers the copper surface with gold to prevent oxidation and bonds at 120 ℃.
• "Power Delivery and Performance of Microbump and Hybrid Bonding 3D ICs" (2022) — DOI: 10.1109/tcpmt.2022.3221025 — Up to 76% performance or 17 mV difference in a design flow comparison, proposing improvements even for the microbump side.
• "Fine-Pitch Face-to-Face 3D System Design Using Die-Specific Placement and Routing" (2019) — DOI: 10.1109/3dic48104.2019.9058901 — Splitting the core into layers at roughly 1 μm pitch, achieving 40% wiring reduction and 19% timing improvement compared to 2D.
• "Process Variation Impact on Hybrid Bonding Interconnects Down to 1.44 μm" (2020) — DOI: 10.1109/eptc50525.2020.9315028 — 6.8 to 1.44 μm test structures, showing alignment error as the common factor for resistance and capacitance.
• "Low-Temperature Direct Bonded Three-Dimensional Structuring for Image Sensors" (2014) — DOI: 10.1149/ma2014-01/37/1412 — Gold-oxide bonding builds a 3D inverter and a 101-stage ring oscillator, optimizing n-type and p-type separately.
• "Copper-Free Wafer Hybrid Bonding for Medical Imaging Sensors" (2020) — DOI: 10.1109/ectc32862.2020.00044 — Titanium-oxide bonding, contact resistance under 1 Ω and capacitance under 2 fF on 3 μm square pads.
• "Impact of Pitch Reduction on Wiring Robustness in 3D Stacked Image Sensors" (2018) — DOI: 10.1109/iedm.2018.8614570 — No thermal cycle or electromigration defects from 8.8 down to 1.44 μm.
• "Recent Progress in Fine-Pitch Wafer Hybrid Bonding Using Copper Interconnects" (2019) — DOI: 10.23919/iwlpc.2019.8913862 — Separating memory and logic to optimize within their respective thermal budgets, exceeding 98% yield on 115,000 links at 4 μm.
• "Mass Production Equipment Application of Die Bonding Based on Simulated Process Variables" (2021) — DOI: 10.1109/ectc32696.2021.00018 — Cutting and handling contaminate the surface. Solved by commercial bonder specifications of ±3 μm/3σ and process flow modification.
• "Fine-Pitch 3D-IC Die-to-Wafer Copper Hybrid Bonding" (2023) — DOI: 10.1109/ectc51909.2023.00178 — 4 μm pitch and 2 μm pads, all 210 chains exceeding 98% yield and passing package-grade reliability.
• "Hybrid Bonding Yield Model and Simulation Reflecting Pad Layout" (2025) — arXiv:2511.05506 (preprint) — Integrates alignment, particles, dishing, roughness, and density into a single framework. The 1,000x refers to calculation speed, not yield.
• "Transition-Era Failure Analysis: Advanced Packaging Industry Survey" (2026) — arXiv:2606.22149 (preprint) — About 100 responses, with hybrid bonding ranking as the most difficult new structure to analyze (54%).
• "Wafer Bonding Pitch Reduction Below 0.5 μm Through Process Innovation" (2023) — DOI: 10.1109/ectc51909.2023.00010 — Combines placement, dielectric, polishing, and alignment, investigating where copper density breaks down the material system.
• "Challenges and Solutions in Cu/SiCN Wafer Bonding Down to 400 nm Pitch" (2023) — DOI: 10.1109/iedm45741.2023.10413829 — 400 nm appears only in the title. Controls alignment with hexagonal lattices and circular pads, analyzing alignment-versus-resistance and yield relationships.
• "Towards Standardization of the Hybrid Bonding Interface: A Study on Direct Bonding Dielectrics" (2024) — DOI: 10.1109/ectc51529.2024.00100 — Compares bonding energy and micro-void density of four dielectric pairs, proposing standardization candidates.
• "Hybrid Bonding for Ultra-High-Density Interconnects" (2024) — DOI: 10.1115/1.4064750 — Sub-0.5 μm showed feasibility while limits below 0.4 μm are being explored (literature review), leaving die handling and standards as open challenges.
• "High-Throughput Two-Step Die-to-Wafer Thermocompression Bonding" (2023) — DOI: 10.1109/ectc51909.2023.00067 — Exceeding 300 units per hour. Concludes that thermocompression is better down to roughly 7 μm bump pitches in 3D stacking and interposers.