If the Board Warps, Nothing Above It Helps — The Bill for a Glass Base and In-Package Light

35 Percent, and the Glass That Breaks Inside

The substrate is a plate that mounts the chip and connects it to the circuit board below, and right in the middle of it is a core that keeps the plate stiff. When this core was changed from resin to glass, the degree to which the component placement deviated from the design value—in other words, the variance in positional accuracy—decreased by 35% compared to plates using a resin core. The amount the plate warped while receiving heat dropped to less than half that of the resin-core plate. They also succeeded in filling the holes penetrating the plate with copper without any gaps, and the resistance of a test circuit connecting those holes in a row remained within ±10% of the initial value even after undergoing reliability tests. These are the values measured and reported to a conference by a substrate company for its prototype (DOI: 10.1109/ectc51687.2025.00178, substrate manufacturer presentation).

A few sentences later in the same paper comes a passage noting that the inside of the glass cracks when the plate is cut. The cause identified by the authors was the difference in thermal expansion between the glass and the buildup resin (the insulating resin applied on top of the core to build up the wiring layers), and the cracking occurred near the boundary between the two. By overcoating the edges with resin to reduce the stress applied to the glass, it was possible to prevent that cracking even after going through the 260-degree reflow process of melting and attaching solder (DOI: 10.1109/ectc51687.2025.00178, substrate manufacturer presentation).

Within a single paper, the gains and the price to pay are placed just sentences apart. This article follows that gap.

For a long time, the substrate was a support. What determined performance was what was placed on it and how, and the plate did its job once it held up the pieces and sent signals downward. Sending signals outside the equipment was also not the package's role. The package is a single mass of components that wraps and protects the chip and connects it to the external circuit board, while the task of converting signals into light to send them far away was handled separately by optical modules plugged into the front panel of the equipment.

Over the roughly 10 years spanned by the cited papers, both of those positions have been shaken together. Therefore, the story of this article is twofold. One is the story of changing the floor on which the pieces sit—in other words, the core of the substrate—to glass, and the other is the story of the path leading out of the package—in other words, pulling the device that converts signals into light right next to the chip. One substrate company describes the background of why the floor became an issue again as follows. As chips grew larger, the ratio of usable chips among those made—in other words, the yield—dropped, and as an alternative, chiplets—which divide chips into pieces and connect them together—and methods of putting chips with different functions into a single package have been developed, demanding larger packages. And they view that in existing packages, because materials with high thermal expansion are used, the mounting accuracy of placing components in the exact spot becomes a problem (DOI: 10.1109/ectc51687.2025.00178, substrate manufacturer presentation). Chiplets, which are silicon pieces made separately and connected together within a single package, are covered in "They Chose Not to Make It One Chip". The floor story and the exit story start from different problems, but they meet later at the point of engraving light paths on the glass plate.

The numbers in this article are of four types: values measured from actual fabrication, values produced by finite element analysis, target values for objects not yet fabricated, and values presented by companies introducing their own technology. Finite element analysis is a method of calculating the flow of force and heat using a computer model that divides an object into tiny pieces. Because a single paper sometimes mentions two types together, the type classification is attached to each sentence rather than the paper.

When a Plate Warps, Precision On It Is Useless

An organic substrate is a chip-mounting plate made by taking a plate of glass-fiber cloth impregnated with resin as a core, and building up wiring layers layer by layer on top and bottom. Think of plywood. The center core handles thickness and stiffness, and the wiring is drawn on thin layers applied to both sides of that core. The chip sits on the topmost layer, and signals pass through the core down to the circuit board on the opposite side.

The time this plate becomes a problem is when heat enters, and there is a value looked at first in that situation. The coefficient of thermal expansion is the value describing how many millionths of its length a material stretches for every 1 degree it is warmed. So the unit is ppm/°C, which is "parts per million per degree." What creates the problem is not a single value, but the difference between two materials. If the values of two fastened materials differ, one stretches more when heated and shrinks more when cooled, building up force at the boundary between the two.

That force expressed in the shape of the entire plate is warpage. Warpage is when a plate formed by laminating different materials together stretches and shrinks by different amounts per material while being heated and cooled, causing a surface that should be flat to curve like a bow. Because a substrate is an item made by laminating different materials, it cannot avoid this property.

As mobile devices have demanded thinner packages, warpage has worsened, and warpage affects the narrowing of the pitch of the contacts attaching the chip and the reliability of the bonding (DOI: 10.1109/tcpmt.2016.2641164). Pitch is the distance from the center of one contact connecting a chip to a chip (or a chip to a plate) to the center of the immediately adjacent contact, a value covered by "Nothing In Between". When a plate bends, the edge contacts may not make proper contact. No matter how precise a piece you place on top, if the place where it is placed shakes, that precision cannot be used.

There are measurements comparing by matching the coefficients of thermal expansion to be equal, showing that low-expansion glass warps less than an organic core. The experiment was like this: glass substrates and organic substrates with a core thickness of 100 micrometers were prepared side by side, the glass side was cut from the panel into 18.4 × 18.4 millimeter pieces and attached with the same silicon chip piece (die) by thermal compression at 260 degrees, and warpage was measured using light interference fringes. The low-expansion glass had lower warpage than an organic core with the same coefficient of thermal expansion, and increasing the coefficient of thermal expansion of the glass increased warpage. The size of the resin (underfill) overflowing to the edge and hardening to fill the gap between the chip and the plate, in other words the size of the fillet, also affected the warpage of the thin substrate, and there was a separate optimal size that minimized warpage most (DOI: 10.1109/tcpmt.2016.2641164, a study presenting both measurements and models).

The core of this comparison is the condition "than an organic core with the same coefficient of thermal expansion." Because the coefficients of thermal expansion were matched to be equal, the difference must have come from other properties. The authors cite a much higher elastic modulus—in other words, stiffness to bend less even when receiving the same force—and thermomechanical stability as the basis for the potential of glass to reduce warpage more than low-expansion organic materials. However, one equipment manufacturer explains the low warpage of glass rather thanks to a relatively low elastic modulus, so the reasons vary from paper to paper (DOI: 10.4071/001c.74577, presentation by an equipment manufacturer).

Another team measured with a different ruler. A 200 micrometer thick glass was placed on a 508 × 508 millimeter panel to build up four wiring layers, and test circuits were made by connecting front and back with through holes of 100 micrometers in diameter. The copper line width and spacing were 8 micrometers. The warpage of this glass was 3 times better compared to an organic substrate (a resin material called BT) with the same 200 micrometer core thickness. However, the authors noted at the end that additional work is needed to develop, refine, and evaluate concerns regarding manufacturability and reliability (DOI: 10.4071/isom-wa15, 2014 demonstration).

The three values that just appeared, 35 percent, under half, and 3 times, are not values measured with the same ruler. The first two are values compared against an organic core by one substrate company, and 3 times is compared against a specific organic core material called BT. The experiment before that even matched the coefficients of thermal expansion to be equal before comparing the remaining properties. If you place the three in a row, it might seem like a single number such as "how much better glass is than organic" would come out, but the comparison targets are all three different.

The organic side, which is the comparison target, had not stood still in the meantime. In 2012, a materials company released two types of thin core materials for mobile devices such as smartphones and tablets, listing the coefficient of thermal expansion in the direction parallel to the plate as 2.8 to 3.3 ppm/°C. In the authors' phrasing, a level similar to the glass-fiber cloth itself. One of those types exceeded 33 to 36 gigapascals at room temperature in flexural modulus, which is the degree of endurance against bending force. When measuring warpage before and after assembly in a structure where packages are stacked on top of packages, these materials showed much lower warpage than existing low-expansion materials (DOI: 10.1109/ectc.2012.6249048, presentation by a materials company).

This fact does not contradict the previous comparison. Because the coefficient of thermal expansion of the organic core had already dropped to a point competitive with glass at least for that application, the remaining difference lay on the side of other properties outside the coefficient of thermal expansion. However, this is a story about thin cores for mobile devices from 2012. It was not measured with the same ruler as the glass substrate papers targeting large packages for artificial intelligence.

What must be asked is not "Does glass beat organic?" but "Under which conditions, based on what does it beat it?" A 2025 review surveying glass core substrates notes that glass is promising in dimensional stability, thermal conduction, and electrical characteristics, and may also be important for bringing light inside the package (co-packaged optics, seen later), before immediately pointing out the bottlenecks to overcome. They are making through-glass vias and filling them with metal, thermal expansion coefficient mismatch, warpage, and handling large glass plates (DOI: 10.23919/nordpac65171.2025.11084260, review).

Drilling Holes in Glass

Glass through-vias are vertical wires made by filling holes drilled straight through a glass plate from top to bottom. They do the exact same job as through-silicon vias ("Fetching Is Slower Than Computing"), which are metal wires like copper filling holes drilled straight through a chip from top to bottom. The only difference is the material being drilled through, and almost all the difficulty of this technology comes from that single difference.

The proposal to use glass here was already made back in 2012. It was a paper suggesting glass as the material for an interposer—a thin plate with dense wiring neatly laid out to hold multiple chips side by side and connect them ("The Bottleneck Was Never Compute"). The starting point was that organic interposers are dimensionally unstable and silicon interposers are expensive. The authors presented a thin glass interposer that could be scaled up to panels over 700 millimeters, and showed that through-vias spaced 50 micrometers apart were possible in glass 180 micrometers thick. And they noted that making small through-holes quickly was the biggest technical barrier to adopting glass for interposers and system substrates (DOI: 10.1109/tcpmt.2012.2204392).

At least on the problem of drilling holes, processing was a bigger stumbling block than the material of glass itself.

In 2014, that processing sped up significantly. Using a method where ultra-short laser pulses modify the entire thickness of the glass all at once and then only those modified parts are rapidly dissolved away with chemicals, it became possible to drill roughly 5,000 holes per second. In glass 50 to 200 micrometers thick, they obtained holes with diameters of 10 to 50 micrometers and a gentle taper of under 5 degrees, depending on the etching time. The same paper noted in its background that metallization—coating the holes with metal—was largely solved, and that making the holes remained the primary stumbling block for glass interposers (DOI: 10.1109/estc.2014.6962711).

An equipment company that commercialized this family of technologies stated that it can achieve a cumulative positional accuracy of ±5 micrometers across an entire 510 × 515 millimeter panel, with aspect ratios (the ratio of depth to diameter) ranging from 1:10 to 1:50. The most important thing in this introduction is the conditional clause. It is that glass is highly reliable both during processing and during operation when it is processed with a technique that does not create defects such as micro-cracks or thermal stress (DOI: 10.4071/001c.74577, equipment maker presentation). That reliability is not guaranteed for glass drilled with processing that creates defects.

The Bill for Glass — It Breaks, and Without Thermal Vias It Sheds Less Heat

The first price of glass is that it breaks. A study that built a simulation model to predict the warpage of glass interposers writes, in the very next sentence after listing the advantages of glass, "Nevertheless, glass is inherently brittle." So the problem consciousness of this study was that the combination of glass and molding resin (the resin that covers and hardens a chip) must be chosen well, and the authors picked apart one by one the effects of five factors on warpage: glass thickness, the thermal expansion coefficient and elastic modulus of the glass, and the thermal expansion coefficient and elastic modulus of the molding resin. These values were produced by finite element simulation, and the validity of the model was confirmed by comparing it with actual warpage measurements of an 8-inch molded glass wafer (DOI: 10.1109/tcpmt.2021.3065647).

So the actual warpage measurements in the previous section and these simulation values cannot be placed side by side. The sample sizes and conditions are different. The values in the previous section were measured by attaching dies to 18.4-millimeter square pieces, and the values in this study are from putting an 8-inch molded wafer into the model.

The instance we saw at the beginning, where glass broke on the inside when slicing the plate to divide it into individual packages, is the same price. The breakage occurred near the boundary between the glass and the buildup resin, and the cause was the difference in thermal expansion between the two (DOI: 10.1109/ectc51687.2025.00178, substrate manufacturer presentation).

What happens when heating and cooling are repeated for a long time was also tested. Through-glass vias with a diameter of 30 micrometers were made at intervals of 120 micrometers in bare glass 100 micrometers thick, and thermal cycling from minus 55 degrees to 125 degrees Celsius was run. In the chain connecting the through-glass vias in a row, not a single electrical failure appeared. However, destructive analysis looking at the cross section through an electron microscope revealed copper peeling and glass cracks (DOI: 10.1109/tcpmt.2017.2691407, actual measurement). Being electrically fine and being structurally fine are different things. However, citing only this crack in isolation is wrong. The authors state that this result matches the thermomechanical model and put forward design and process recommendations. Rather than the conclusion to fold up on glass, it is a conclusion to narrow the conditions for using glass.

Another test also comes in two layers. When an interposer was made with glass of two compositions having thermal expansion coefficients of 3 and 8 ppm/°C and cycled 1,000 times from minus 40 degrees to 125 degrees Celsius, there were no failures in a chain connecting 400 through-vias. Yet a separate test yielded a different result. This was a test that applied voltage to copper structures with a 10-micrometer line width, gave accelerated stress for 96 hours, and then measured the leakage current leaking between separated structures. As a result, the glass with a thermal expansion coefficient of 8 ppm/°C required a barrier layer to prevent copper from migrating into the glass (DOI: 10.1109/ectc.2015.7159664, actual measurement). Glass can have its thermal expansion coefficient adjusted to a desired value by changing its composition, but the authors write that the impact of composition changes on long-term reliability must be carefully weighed. In this test, the higher thermal expansion coefficient glass was such a case.

When the bonding method changes, the problem grows again. According to a finite element model run with all-copper bonding—which directly connects chips and glass substrates copper-to-copper without solder—placed at 10-micrometer intervals, thermal expansion mismatch could be managed with compliant solder bonding, but with all-copper bonding, system-level reliability issues become more complex. Bonding that directly attaches metals without solder is covered in detail in "Nothing In Between". The risk spotted by the model was interfacial cracking in the wiring layers inside the chip. The authors write that this model allows us to peer into how the thermal expansion coefficient of the glass core and the choice of gap-filling material affect that risk, and to select a combination that simultaneously satisfies chip-level and board-level reliability (DOI: 10.1109/ectc51529.2024.00394, finite element model).

The final price is heat. A study comparing the thermal performance of glass and silicon interposers for mobile device use begins by stating conventional wisdom as it is. It is that silicon is a good thermal conductor and glass is a poor conductor, and it is well known that this point can make glass unsuitable as a packaging material. This study ran a calculation model incorporating values of the effective thermal conductivity of the glass substrate measured with an infrared microscope, and the results are slightly different from conventional wisdom. When through-vias—which act as paths for heat to escape—are inserted, the temperature of the junction inside the chip drops by about 60% in the glass interposer and 45% in the silicon interposer, bringing both to acceptable levels. Because these two numbers are each compared against themselves without thermal vias, this does not mean glass is better than silicon by 60 to 45. Glass also had an advantage that silicon lacks. Thermal insulation between the logic chip and the memory chip is much better. When placed inside a case mimicking a mobile device, the two materials performed similarly as long as thermal vias were present (DOI: 10.1109/ectc.2013.6575767, calculation model).

When the comparison target changes, the evaluation of the same property flips. That the 2025 review seen earlier picked glass's thermal conduction as an advantage is a story compared with organic substrates, and "poor conductor" is a story compared with silicon.

The Exit — The Cost of Dragging Far with Electricity

Now for the second story: the path of signals heading out of the package. A semiconductor company recently packaged a switch chip—which routes data between servers in a data center—and optical circuits together in the same package for the first time, noting in the background that data center IP traffic doubles every 2.5 years. This means the connection bandwidth, or the amount of data that can be moved per unit of time ("Fetching Is Slower Than Computing"), must grow at that same rate. Yet as data speeds increase, the distance electrical links can travel decreases, while energy efficiency does not improve significantly (DOI: 10.1117/12.2577314, manufacturer announcement).

Trying to send data faster means it cannot go as far, nor does the electricity spent per bit become cheaper. The same announcement explains the effect of the solution like this: placing optics close to the chip shortens the electrical channels, reducing the power required for the circuits that push out signals, which in turn reduces total power consumption. The same announcement immediately notes that placing optics right beside electronic circuits can still be difficult.

Co-packaged optics is an approach that places the devices which convert electrical signals into light and back inside the same package as the switch or processor. Those devices were originally housed in finger-sized modules plugged into the front panel of equipment, and signals crossed over the circuit board electrically from the chip to that module. Co-packaged optics involves taking that module apart and moving it to a seat right next to the chip.

Where power is saved becomes clearer from the circuit side. When modules plugged into the front panel exceed 100 gigabits per second per lane, they must use power-hungry digital signal processor chips to revive signals lost in the channel. Co-packaged optics allows replacing those chips with linear amplification circuits, which reduces power, cost, and latency all at once. What this team produced is a 4-channel front-end circuit for such linear driving. What the abstract sketched as the seat for that circuit is an optical engine—a bundle of components that converts electrical signals into light and back. The structure puts four 4-channel transceivers into a single optical engine, attaching 16 fiber channels running at 112 gigabits per second to the edge of the chip.

The final sentence of the same abstract notes the remaining loss. It states that the equalization circuit embedded in the circuit—meaning the circuit that corrects weakened signals—must compensate for a channel loss of 10 to 12 decibels between the switch and each optical engine (DOI: 10.1109/a-sscc58667.2023.10347914). A decibel is a unit that records how much a signal has weakened, which we examine in detail later. Even in this design, the electrical section has only grown shorter, not disappeared, and a loss of 10 to 12 decibels remains in that shortened space.

By packing a single 14-nanometer die of an FPGA—a chip whose circuit configuration can be changed later—along with five optical input/output chiplets into a single package, they achieved 5.12 terabits per second. The number before "nanometers" is a process generation number that does not indicate the length of a component ("What Is "3 Nanometers" the Length Of?"). The authors note this as the first realized and verified 5.12-terabit co-packaged FPGA (DOI: 10.1109/vlsitechnologyandcir46769.2022.9830221). Another team used a government project to connect three bundles of optical circuits with a silicon bridge and butt-coupled three fiber bundles to the side of the chip. There were 56 couplers in total, with a spacing of 127 micrometers. The authors note this as a successful proof-of-concept assembly (DOI: 10.1109/ectc51687.2025.00061). Having built something is different from being able to sell it, and the authors maintain that distinction.

1.7 and 0.034 — They Are Not Measured with the Same Ruler

The two numbers in the section title are the easiest pair to misread in this article. The first number is the electrical energy required to move a single bit of data (picojoules/bit), and the second number is the degree to which light weakens as it passes through glass light paths every centimeter (decibels/centimeter). The smaller both are, the better, and both look like the "cost of moving a signal," but the former counts the electricity used by the circuit, and the latter counts the light lost inside a single component. Therefore, these two numbers can neither be compared nor added together. The fact that the second number is much smaller does not mean that light is better than electricity. The electricity used by a link must be measured in picojoules/bit, and the signal strength lost must be measured in decibels separately, and even within each of the two units, what is counted differs from value to value.

Energy per bit is the electrical energy required to move a single bit of data from one side to the other, divided by the number of bits moved. One picojoule is one-trillionth of a joule. A smaller value is better, but what must be looked at before the magnitude is what was counted. Depending on whether the laser that creates the light was included, the value for the same link changes.

1.7 picojoules/bit is the value highlighted in the title by a 112-gigabit-per-second transceiver built with a 7-nanometer FinFET process. FinFET is the transistor structure with channels standing up like fins, which we saw in "A Transistor Is a Switch". This value is for an electrical link, not an optical one, and its use is in-package communication. The abstract does not state what was counted for this value either (DOI: 10.1109/isscc42613.2021.9365752). It is easy to think of it as a baseline to compare with light, but it is not the same section that light aims to replace.

About 2 picojoules/bit is a value obtained by designing an on-chip link using 28-nanometer and 14-nanometer processes with wavelength division multiplexing—meaning carrying different signals on light of multiple wavelengths and sending them down a single path—and co-simulating electronic circuits and optical devices. It is the optimal point at 25 gigabits per second with an error rate of 10⁻¹², and is a high value because it includes the power for temperature control of the laser and the ring (a ring-shaped optical device) (DOI: 10.1109/jlt.2016.2542065, co-simulation model).

3.5 picojoules/bit is the value for a 200-gigabit-per-second wavelength-division transceiver where electronic circuits and optical circuits are built together on the same wafer. The reason this team chose that structure is that building two chips separately and attaching them creates unwanted electrical capacitance (parasitic capacitance) due to electrostatic protection circuits and input/output pads, which degrades signal quality and energy efficiency (DOI: 10.1109/a-sscc60305.2024.10848817). However, the abstract does not state this value, nor whether the laser was counted. It is a number that appears only in the title.

About 1 picojoule/bit has a different character. Measured by a team that developed a 200-gigabit-class vertical-cavity surface-emitting laser that emits light upward from the chip surface, this is the value for the device. The 3-decibel bandwidth exceeded 35 gigahertz, the relative intensity noise—which is the fluctuation in light intensity—was below −152 decibels/hertz, and there were no uncorrectable errors across 50 meters of OM4-specification optical fiber. Here, bandwidth is the speed of the signal that the laser can follow, expressed as a frequency, which is a different value from the data bandwidth mentioned earlier. On the other hand, 1 picojoule/bit is the value stated to be achievable by the close-proximity optical structure proposed by the authors using that device, and the authors add that it is the highest efficiency among optical interconnects. This structure places the light near the package rather than inside it (DOI: 10.3390/photonics13010090).

2.5 picojoules/bit and under 1 picojoule/bit are values put forward by a European collaborative project, and all are future-oriented. They are designed to support 112 gigabits per second per channel, the 22-nanometer process circuit has the potential to achieve under 1 picojoule/bit, and total consumption is expected to be lowered to 2.5 picojoules/bit. 6.4 terabits per second per port is also a target value of the same character (DOI: 10.1117/12.3079256, roadmap target).

If you put these five sets in a row and read them as "light is getting better than electricity," it is wrong in several places. Electricity and light, actual measurements and simulations and targets, values counting only the transceiver versus values counting up to the laser, values counting the entire link versus values counting only the circuit, and inside the package and near the package are mixed together. To answer "When does light beat electricity?", these rulers must be aligned into one, but among the papers cited in this article, there is no ruler aligned that way.

Terabits are the same. 5.12 terabits is the total output of a single package, 112 gigabits is the target for a single channel, and 6.4 terabits is the target for a single port.

The decibel side, which describes loss, is more confusing. Insertion loss is the value, expressed in decibels, of how much a signal has weakened while passing through a certain section. 3 decibels means about half is left, and 10 decibels means only one-tenth is left. Therefore, for this value, you must look at "which section" it is before its magnitude. A path created to keep light trapped and flowing is called a waveguide, and the value after passing 1 centimeter of waveguide, the value crossing from the fiber to the chip, and the value passing through the entire link are all written in the same unit.

Waveguides can also be made inside glass. By allowing silver ions to permeate the glass surface and raising only the refractive index—meaning the degree to which light slows down and bends—of that area, light is trapped and flows inside it. Research refining this method for co-packaging produced a waveguide with a propagation loss of 0.034 decibels/centimeter following the waveguide, and the coupling loss crossing between the optical chip's waveguide and the glass waveguide was less than 0.5 decibels. This waveguide comes with a requirement that it must withstand 85 degrees for 5 years, and the authors report that they met that requirement using alkali glass and a barrier layer. The side with the condition attached is 0.5 decibels. This is the value when the barrier layer is thinner than 200 nanometers (DOI: 10.1109/ectc51529.2024.00023, actual measurement).

Earlier research in the same series wrote the values for three sections side by side. They are a propagation loss of 0.08 decibels/centimeter, a coupling loss of 0.3 decibels entering the waveguide from the fiber, and a coupling loss of 0.25 decibels crossing from the glass waveguide to the silicon optical waveguide (DOI: 10.1109/icsj47124.2019.8998659). All are in decibels, but the measurement locations differ.

There are also values for the spot where the fiber is attached. A team using glass optical bridges reported that the average loss from the fiber to the optical chip was 1.41 decibels, and the average loss of the detachable connector itself was 0.33 decibels (DOI: 10.1109/jlt.2023.3285149). Another team cut a glass wafer with a laser to make the flatness of the 6.5-millimeter section where the connector touches less than 1 micrometer, and made connector pins self-align into the laser-cut spots. Instead of active alignment, which matches positions while actually flowing light, it is passive alignment that fits into place just by plugging it in. Measured after plugging and unplugging the connector, this passive alignment method increased coupling loss by an average of 0.19 decibels compared to active alignment (DOI: 10.3389/aot.2023.1244009). This is the amount increased, not the value of the total loss.

The most easily confused pair is separate. The 10 to 12 decibels in the exit section are written in the same units as the values given here, but they are the loss of the electrical channel. All eight values just listed are values for places where light passes, of which 0.034 and 0.08 are values per 1 centimeter of waveguide, and 0.5, 0.3, 0.25, 1.41, 0.33, and 0.19 are values per single boundary crossing. Pairs with the same unit that you gloss over are more dangerous than pairs that stand out because their units differ.

If You Attach the Fiber, You Can't Fix It

One place where this technology gets stuck is the moment a fiber is attached. Among the methods of receiving light head-on from the side of the chip, the industry's top-level method at the time that paper was written was to etch a V-shaped groove in silicon and attach the fiber directly. The paper pointing out this problem notes that because there is no rework capability at all, if an error occurs in this process, the entire package is lost along with the expensive silicon invested in it. Problems sometimes multiply. As the number of optical chips attached to a single package increases, the overall yield drops by that much (DOI: 10.1109/jlt.2023.3285149). Packages with directly attached fibers cannot be repaired, and the risk multiplies as the number of optical chips increases.

The answer provided by the same paper is the detachable connector we saw earlier. By attaching a glass optical bridge inscribed with waveguides and alignment structures to the optical chip at the die stage to make an optical module, each module is tested one by one and only the working ones are put into the package. Then the overall yield is no longer multiplied by the number of optical modules. The principle of using only what has been tested and confirmed to be working before attaching the pieces—known as known-good-die (They Chose Not to Make It One Chip)—is repeated as-is in optics. As a bonus, the fiber is never permanently attached to the expensive silicon.

There is also a place where glass and light meet on a single plate. An attempt to put electrical wiring and optical wiring into a single substrate by combining a machining technology that drills through glass without defects and a laboratory process handling ion-exchange waveguides and passive alignment was reported in 2026. What was measured was the positional accuracy and diameter variation of the through-holes, and the surface roughness of the excavated groove (cavity), and the authors record this as a demonstration of the feasibility of a hybrid substrate platform (DOI: 10.1117/12.3080591).

The difficult field challenges pointed out by an OSAT company are as follows. When placing a fiber bundle on an optical chip, it is active alignment versus passive alignment, receiving light from above in a grating versus head-on from the side, and that both electrical performance and thermal performance are difficult challenges. Among them, the one for which this company even provided a process solution was the warpage of a co-packaged structure made with a fan-out structure where wiring is spread widely to the outside of the chip. This applies separately when attaching the wafer and when attaching the package (DOI: 10.1109/impact67645.2025.11281694, OSAT company presentation). The floor story and the exit story meet here. Even in packages that incorporate light, warpage was an assembly task that had to be solved separately.

Temperature also shakes the path of light. Co-packaging is the work of placing optical components next to a hot chip, and those components are made of materials with different coefficients of thermal expansion. In a module that bends and transfers light using micro-mirrors, this problem came out in numbers. In a calculation solving thermal deformation and light propagation together using the finite element method, at a wavelength of 1550 nanometers from 15 degrees to 85 degrees, the coupling efficiency exceeded 85%, and the average coupling loss difference between 20 degrees and 85 degrees was 0.49 decibels. When the same team actually manufactured it and measured it at 25 degrees, 55 degrees, and 85 degrees, the average loss difference in the C-band, a wavelength range commonly used for optical communications, was 0.80 decibels (DOI: 10.1109/jlt.2023.3283023).

These two values were also not measured with the same ruler. The calculation compared two points, 20 degrees and 85 degrees, at 1550 nanometers, and the actual measurement compared 25, 55, and 85 degrees as the C-band average. Because the conditions differ, the two values cannot be directly compared, but in this module, the average coupling loss changed both in calculation and in actual measurement as it passed through the temperature range. The coupling losses listed earlier are values whose abstracts do not disclose the measurement temperature, so it is difficult to assume that those values remain unchanged right next to a hot chip.

So When Does It Become a Net Gain?

In 2018, a comparative analysis weighing the architecture of bringing optical fibers all the way to the server against the traditional copper-linked structure ended with this: the emerging low-cost co-packaged approach, when combined with high-radix switches featuring many ports, will likely tilt the scale toward optical fibers (DOI: 10.1109/ps.2018.8751280). There are two conditions, and the conclusion is a possibility. The title itself was a question: "Are We There Yet?"

The remaining question is this. When is it a net gain to bring light all the way inside the package, despite paying all these costs? The cited papers offer different answers.

Another paper from the same period does not place co-packaging as the sole answer. It argues that the pressure of switch speeds and port counts rising together is pushing forward all at once: new pluggable module formats, optics mounted on the board, and co-packaging with the switch chip (DOI: 10.1364/ofc.2019.th3a.2).

Other choices are proposed in 2026 as well. What the vertical-cavity surface-emitting laser team presented earlier was a structure that placed light near the package rather than inside it (DOI: 10.3390/photonics13010090). The authors base this on the point that light can travel farther than copper and tie clusters together in a larger network. This reason alone does not settle whether light must necessarily go all the way inside the package.

A final report for a government project aiming for a coherent approach—which carries signals not just in the intensity of light but also in its phase—lists several firsts, then notes that while the program met its speed target of 112 gigabits per second, it did so at a higher error rate than targeted (DOI: 10.2172/2221777, project final report). The progress of the technology is not entirely smooth.

A commentary (preprint) from 2026 addresses this question most directly. The authors argue that co-packaging should not be viewed as component-level optimization, but as an architectural decision that redraws the boundaries among photonics, electronics, and system design. They add that the closer light gets to the computing device, the more packaging, thermal management, and system-level robustness come to dominate performance and scalability. Heterogeneous integration strategies that pack pieces with different properties and fabrication processes into a single package ("They Chose Not to Make It One Chip") and new packaging platforms rewrite the scaling rules of AI systems, but in the process, they frequently introduce trade-offs that are underestimated by device-centric analyses. Thus, the deciding factor they picked was not performance figures. They write that standardization, serviceability, and co-design that accounts for heat together will determine whether co-packaging can move from initial deployment to widespread adoption (arXiv:2603.21313v1, preprint commentary).

Serviceability is the degree to which a broken part can be repaired or replaced, and the problem that attaching fibers directly, as we saw earlier, makes them unrepairable falls precisely under this category.

To summarize: Low-thermal-expansion glass warps less than organic cores with the same coefficient of thermal expansion, is dimensionally stable, and can be made into large panels. However, the task of handling those large panels itself is on the bottleneck list. Moreover, glass breaks, conducts heat worse than silicon unless thermal vias are inserted, and reliability issues mount again if the bonding method changes. Light can travel distances electricity cannot and can eliminate signal-processing chips. However, if fibers are attached directly side by side using the method from the time that paper was written, it becomes impossible to repair—and the detachable connector proposed by that paper targets precisely that spot—while coupling losses vary with temperature, and the numbers used in comparisons are measured with different rulers. Furthermore, the opposing side has not stood still either. The coefficient of thermal expansion of organic cores has fallen to the level of glass-fiber cloth, at least in thin cores for mobile devices. Although electrical transceivers that move 112 gigabits per second at 1.7 picojoules per bit over short distances inside a package have emerged, that same paper also points to silicon photonics and chip co-integration as the path to scaling package throughput beyond the limits of electrical interfaces.

Yet, the reason these two attempts run together is read by this article as follows: the locus that determines performance has dropped yet another layer deeper. In the past, performance was about how small you could make transistors; after that, it was about how you joined pieces together. Now, performance even includes how flatly the floor beneath those pieces holds up and where the exit for signals is located.

"They Chose Not to Make It One Chip" stated that as long as the reason to cut lies in physics, there is no final destination to cutting. In this article, the same point can be rephrased like this: No matter how precisely you build from the top, that precision can only be utilized as much as the floor allows, and no matter how fast you compute, the results only emerge as fast as the exit lets them out. The remaining debate is not whether glass or light is right, but how much price we will pay for those two spots and when that price turns into a net gain.

Source Papers

• "Development of Glass Core Build-up Substrate with Glass Through Vias" (2025) — DOI: 10.1109/ectc51687.2025.00178 — Substrate vendor presentation. 35% lower positional accuracy deviation and less than half the dynamic warpage compared to organic cores. The cause of intra-glass breakage during dicing is CTE mismatch with the build-up resin.
• "Experimental and Theoretical Evaluation of Thin Glass Substrates for Low Warpage" (2017) — DOI: 10.1109/tcpmt.2016.2641164 — Combined experimental measurements and modeling. Low-CTE glass exhibits lower warpage than organic cores of the same CTE, and increasing CTE increases warpage.
• "Development of Low-Cost Glass Interposer" (2014) — DOI: 10.4071/isom-wa15 — 200 μm glass on a 508×508 mm panel. 3 times better warpage compared to organic substrates (BT) of the same core thickness. Manufacturability and reliability require additional work.
• "Ultra-Low Thermal Expansion Material for Thin Core Packages" (2012) — DOI: 10.1109/ectc.2012.6249048 — Material vendor presentation. Thin core material for mobile devices. CTE of 2.8–3.3 ppm/°C (comparable to glass fiber cloth) and flexural modulus of 33–36 GPa, with significantly lower warpage than existing low-CTE materials.
• "From Organic Core to Glass Core Substrates — The Journey of IC Substrates Supporting AI and HPC" (2025) — DOI: 10.23919/nordpac65171.2025.11084260 — Review. Benefits of glass cores and relevance to CPO. Bottlenecks = TGV manufacturing and metallization, CTE mismatch, warpage, large-area handling.
• "Low-Cost Thin Glass Interposer as an Alternative to Silicon and Organic Interposers" (2012) — DOI: 10.1109/tcpmt.2012.2204392 — Scaled up to 700 mm panels. High-speed formation of small holes is the biggest barrier to adopting glass.
• "High-Speed Glass Through Via Manufacturing Technology for Interposers" (2014) — DOI: 10.1109/estc.2014.6962711 — Laser-induced chemical etching at roughly 5,000 holes per second, 10–50 μm diameter, taper under 5°.
• "Panel-Level Glass Substrate Manufactured Without Design Constraints by LIDE" (2023) — DOI: 10.4071/001c.74577 — Equipment vendor presentation. Cumulative ±5 μm on a 510×515 mm panel, aspect ratio of 1:10 to 1:50. Subject to the condition when processed with a defect-free manufacturing technology.
• "Finite Element Model for Warpage Evaluation of Glass Interposer Substrate Packages" (2021) — DOI: 10.1109/tcpmt.2021.3065647 — Finite element simulation. Glass is inherently brittle. Cross-verified with physical measurements of 8-inch molded wafers.
• "Reliability of Copper Through Vias in Bare Glass Interposers" (2017) — DOI: 10.1109/tcpmt.2017.2691407 — Physical measurements. Zero electrical failures during thermal cycling from −55 to 125 °C, but failure analysis revealed copper delamination and glass cracking. Results match thermomechanical models and provide design and process recommendations.
• "Glass Through Vias and Reliability Aspects" (2015) — DOI: 10.1109/ectc.2015.7159664 — Physical measurements. 400 TGV chains passed 1,000 cycles without failure. In separate HAST testing, glass with a CTE of 8 ppm/°C requires a Cu migration barrier layer.
• "Chip-Package Interaction of Electroplated Copper Joints on Glass Substrates" (2024) — DOI: 10.1109/ectc51529.2024.00394 — Finite element model. CTE mismatch is managed with solder but becomes more complex with electroplated copper joints. The authors write that the model allows selecting combinations that simultaneously satisfy chip and board reliability.
• "Thermal Performance Comparison of Glass Interposers and Silicon Interposers" (2013) — DOI: 10.1109/ectc.2013.6575767 — Computational model. For mobile device applications. Adding thermal vias drops junction temperatures by roughly 60% for glass and 45% for silicon compared to when each lacks them. Glass provides superior logic-memory thermal isolation. Inside the casing, they are similar.
• "Silicon Photonic Integrated Circuits Co-Packaged with Switch Chips" (2021) — DOI: 10.1117/12.2577314 — Manufacturer presentation. While electrical link reach decreases at high data rates, energy efficiency does not significantly improve. Traffic doubles every 2.5 years.
• "4×112Gb/s PAM-4 Silicon Photonics Frontend for Linearly Driven Co-Packaging" (2023) — DOI: 10.1109/a-sscc58667.2023.10347914 — What this paper presents is a 4×112 Gb/s linearly driven frontend. Beyond 100 Gb/s per lane, pluggables require power-hungry DSPs. The built-in CTLE must equalize 10–12 dB of channel loss between the switch and the optical engine.
• "5.12Tbps Co-Packaged FPGA with Silicon Photonics Input/Output" (2022) — DOI: 10.1109/vlsitechnologyandcir46769.2022.9830221 — 14 nm FPGA die + 5 optical I/O chiplets. Described by the authors as the first realized and verified 5.12 Tbps co-packaged FPGA.
• "Co-Packaged Assembly Demonstration for Fiber-Based Optical Connections" (2025) — DOI: 10.1109/ectc51687.2025.00061 — Proof of concept. 3 sets of optical circuit bundles, 3 fiber bundles, 56 couplers at a 127 μm pitch.
• "1.7pJ/b 112Gb/s In-Package Communication Transceiver in 7nm FinFET" (2021) — DOI: 10.1109/isscc42613.2021.9365752 — Physical measurements. Electrical link intended for in-package communication.
• "Scaling Trends of PJ/bit WDM Optical Interconnects in CMOS SOI and FinFET Technologies" (2016) — DOI: 10.1109/jlt.2016.2542065 — Co-simulation model. WDM links on a chip. Optimum around 2 pJ/b at 25 Gb/s, including laser and ring tuning power.
• "A 200Gb/s, 3.5pJ/bit Monolithic WDM Silicon Photonics Transceiver for Chiplet Optical I/O" (2024) — DOI: 10.1109/a-sscc60305.2024.10848817 — The problem statement is that attaching separate chips introduces ESD and I/O pad parasitic capacitance. 3.5 pJ/bit appears only in the title, and the abstract does not state the included scope.
• "Development of 200G Vertical-Cavity Surface-Emitting Lasers and Proposal for Close-Proximity Packaged Optics" (2026) — DOI: 10.3390/photonics13010090 — Physical measurements showing −3 dB bandwidth >35 GHz, RIN < −152 dB/Hz, error-free over 50 m of OM4. Authors' claim that the proposed close-proximity packaged optics achieve roughly 1 pJ/bit. Near the package, not inside it.
• "2.5D Co-Packaged Optics Solution Targeting 6.4Tb/s per Port" (2026) — DOI: 10.1117/12.3079256 — Roadmap goals. Designed to support 112 Gb/s/channel, potential for under 1 pJ/bit, with 2.5 pJ/bit expected overall. All future tense.
• "Ultra-Low-Loss Ion-Exchanged Waveguide in Optimized Alkali Glass for Co-Packaged Optics" (2024) — DOI: 10.1109/ectc51529.2024.00023 — Physical measurements. Propagation loss of 0.034 dB/cm. Alkali glass and blocking layers meet the requirement of 85 °C for 5 years. Coupling loss <0.5 dB is the value when the blocking layer is <200 nm.
• "Single-Mode Glass Waveguide Substrate for Optical Integrated Circuit Packaging" (2019) — DOI: 10.1109/icsj47124.2019.8998659 — Propagation loss of 0.08 dB/cm, fiber coupling of 0.3 dB, silicon waveguide coupling of 0.25 dB.
• "Detachable Optical Chiplet Connector for Co-Packaged Optics" (2023) — DOI: 10.1109/jlt.2023.3285149 — In edge coupling, direct attachment of silicon V-grooves is not reworkable, meaning an error results in losing the package and silicon entirely, with yields multiplying by the number of optical chips. Fiber-to-PIC is 1.41 dB, detachable connector is 0.33 dB.
• "Ultrafast Laser Processing of Glass Waveguide Substrate for Multi-Fiber Interconnection" (2023) — DOI: 10.3389/aot.2023.1244009 — Flatness under 1 μm across a 6.5 mm connector section. After mating and un-mating the connector, passive alignment shows an average coupling loss increase of 0.19 dB compared to active alignment.
• "Panel-Level Co-Packaging Enabled by Precision Glass Processing and Optical Integration" (2026) — DOI: 10.1117/12.3080591 — Feasibility demonstration. Combining glass processing, ion-exchanged waveguides, and passive alignment to integrate electrical and optical wiring on a single substrate. Measured metrics include via accuracy and cavity roughness.
• "Co-Packaged Optics Solutions and Technical Challenges for Silicon Photonics" (2025) — DOI: 10.1109/impact67645.2025.11281694 — OSAT vendor presentation. Active/passive alignment of fiber bundles, grating coupling versus butt coupling. Warpage control in fan-out CPO.
• "Thermal Characteristics of Micro-Mirror Optical Redistribution Layers for Co-Packaged Optics" (2023) — DOI: 10.1109/jlt.2023.3283023 — Finite element analysis and physical measurements. Coupling efficiency exceeding 85% from 15 to 85 °C. The calculated 0.49 dB (at 20/85 °C and 1550 nm) and the measured 0.80 dB (average across 25, 55, 85 °C in the C-band) cover different ranges.
• "Fiber to the Server — Have We Reached It Yet?" (2018) — DOI: 10.1109/ps.2018.8751280 — Comparative analysis. Low-cost co-packaging combined with high-radix switches is likely to tilt the scales toward optical fiber.
• "The Evolution of Pluggable Optical Modules, and What Lies Beyond" (2019) — DOI: 10.1364/ofc.2019.th3a.2 — Switch speed and port count pressures are pushing all of new pluggable form factors, on-board optics, and co-packaged optics forward.
• "QRock — Coherent Wavelength Switch Co-Packaged Optics Shaking Up Datacenters and HPC" (2023) — DOI: 10.2172/2221777 — Project final report. The 112 Gb/s speed target was achieved, albeit at a higher error rate than targeted.
• "3D Optoelectronics and Co-Packaging — Deployment Stalls While Solving the Wrong Problems" (2026) — arXiv:2603.21313v1 (preprint) — Commentary. CPO is an architectural decision, not a component optimization. As optics move closer to compute, packaging, thermal management, and robustness dominate. Standardization, serviceability, and thermally aware co-design dictate adoption.