Turn the Power Around and the Heat Gets Trapped — The Bill for Grinding Away the Silicon Under the Transistors

Same Row in the Same Table

There is a simulation study that designed two types of CPUs targeting nodes below 2 nanometers, and tested five structures for supplying electricity to them in sequence (DOI: 10.1109/iedm50854.2024.10873426, design and evaluation simulation). A node is a name given to a generation of semiconductor manufacturing (What Is "3 Nanometers" the Length Of?). One of the five was the traditional structure supplying electricity from the front, and four were structures supplying it from the back of the wafer.

A wafer is a thin, round silicon plate used to make chips (Photolithography), and transistors are built on one side of it. A transistor is a tiny switch turned on and off by electricity (A Transistor Is a Switch). The side where the transistors are placed is the front, and the opposite side is the back.

Among the five structures, the electrical performance was best in the structure that made a small connection, namely a contact point connecting wires, directly from the back to the bottom of the transistor. Compared at the operating temperature of the chip in this simulation, the voltage lost until the electricity reached its destination was limited to 8.7% of the front-side structure. This means it was 91.3% smaller.

A few lines above in the same abstract, that structure appears once more. Among the five, the temperature of the hottest spot was the highest. A hot spot is a narrow area on a chip that has become uniquely hot in just one part. The lifespan and operating limit of a chip are determined not by the average temperature, but by a single hottest point. The hot spot temperature of this structure was 14% higher than that of the front-side structure, and the authors attribute the reason to grinding the wafer extremely thin (DOI: 10.1109/iedm50854.2024.10873426, simulation).

If you put the five structures as five rows in a single table, the row where electricity flowed best was the hottest row. This article follows the invoice for that trade-off.

The conventional wisdom until then was like this. The step of stacking metal wiring layers on top after making the transistors is the Back-End-of-Line (BEOL) process (After Moore's Law). All the wiring stacked that way is on the front, and power could just come down riding the thick lines on the upper floors among them. How transistors were made was performance, and feeding electricity was secondary.

Most of the evidence collected in this article is simulation, and things actually made and measured are a minority. The calculation methods are finite element analysis, which divides an object finely to calculate heat and force; TCAD, which calculates a single device entirely using physical laws; thermal SPICE, which solves temperature like an electrical circuit; and evaluations run on chip design tools. Things actually made and measured are to the extent of mass-produced SRAM (small, fast memory placed inside processors), process demonstrations of grinding wafers, test chips embedded with heaters and temperature sensors, and heat sink thermal tests. Therefore, below, we note for each numerical value whether it is a calculation or a measurement.

There is a separate point to be careful about with temperature numbers. The abstract often does not clarify whether a sentence stating "the temperature rose by N%" refers to the ratio of the temperature itself, or how much more it rose than the ambient temperature. Only one paper clarifies this, and we note that the rest do not clarify it.

100 Millivolts Eats 500 Megahertz

Voltage drop is the phenomenon where electricity loses force as it flows along a wire with resistance, arriving at a lower voltage than when it started. It is commonly called IR drop, and the "lost voltage" mentioned in the previous section is this. It decreases if you make the wires thicker or shorter. However, the space to place thick power lines inside a chip is the same space where signal lines need to pass.

Clock speed is the pace at which a processor works, in other words, its operating frequency (Why Did the Clock Stop at 4 GHz). When the voltage drop caused by the power distribution network blocking current reaches 100 millivolts (a millivolt is one-thousandth of a volt), the target clock speed can be shaved down by up to 500 megahertz (DOI: 10.1109/impact56280.2022.9966707, characterization and modeling using a RISC-V CPU as a case study). According to the authors' conversion, for a 1-gigahertz CPU, this is a magnitude that causes performance to plummet by half.

The package outside the chip (the shell encasing the chip), the board, and the voltage regulator module also add up to 5.8% more voltage drop. For a 1-volt supply, that is 0.058 volts. That alone can shave down the target clock speed by up to 250 megahertz more (DOI: 10.1109/impact56280.2022.9966707).

This problem has grown because the current that needs to be delivered has increased. A 2010 paper projected that high-performance chips would emit over 100 watts per square centimeter and demand a supply current exceeding 100 amperes (DOI: 10.1109/ectc.2010.5490755, projections from that time). The larger the current, the greater the voltage lost on the same wire.

The thick lines carrying that current are on the front side. A study covering the 2-nanometer node points to the congestion of front-side routing layers as a challenge brought by miniaturization (DOI: 10.1109/iedm19574.2021.9720528, the authors' problem statement). If you make the power lines thicker, the space for signals to travel decreases; if you make them thinner, the voltage drops.

There is also a loop in the opposite direction. Power density is the power used per unit area of a chip (Why Did the Clock Stop at 4 GHz). An invited talk summary outlining logic scaling in the angstrom era notes that if voltage drop decreases, the operating voltage can be lowered, which in turn lowers power density and generates less heat (DOI: 10.1149/ma2026-01221255mtgabs, invited talk summary—the authors' expression is "can"). Electricity and heat have been tied in a single loop from the start.

Feeding Power from Behind

In 2022, a research team flipped a wafer over and ground down its back side. This continued until the final silicon thickness was under 500 nanometers (DOI: 10.1109/ectc51906.2022.00244, fabrication and measurement). Wafer thinning is a process that grinds down the back side of a finished silicon plate, making it thin—from several tens to over a thousand times thinner than its original thickness.

Backside power delivery is a method where the wiring that feeds electricity to the transistors is stripped from the front side and moved to the back side of the wafer, leaving the front side exclusively for signal wiring. It is like having power lines and communication cables attached together along one wall of a building, and then tearing off only the power lines and moving them to the opposite wall. Instead of the two lines competing for space, construction work is created that makes the opposite wall newly usable.

The vertical pathways connecting the front and back are through-silicon vias, which are holes drilled straight through the chip from top to bottom and filled with metal (Fetching Is Slower Than Computing). Here, because their diameter is hundreds of nanometers, they are called nanovias. A destination for those pathways to land on is also needed. Buried power rails are power lines that used to sit on the wiring layer above the transistors, but are now buried by digging down into the silicon beneath the transistors. In terms of the same building, this is like burying the ceiling plumbing beneath the floor to leave the ceiling empty.

That research team drilled nanovias from the back side to land on these buried rails, and the alignment error was smaller than 10 nanometers. Alignment error is the degree of actual misalignment between points that should meet vertically (Nothing In Between). They filled the pathways with tungsten, cobalt, and ruthenium to measure the resistance, and the measured values matched the simulations well (DOI: 10.1109/ectc51906.2022.00244).

A FinFET with wiring connected to the buried rails from both the front and back sides was also actually fabricated. A FinFET is a transistor with its channel set up like a fin so that the gate wraps around three sides (A Transistor Is a Switch). In this device, the backside pathway was about 323 nanometers deep, and the buried rail resistance did not change even after the backside process (it decreased by 26–29% when tungsten filling was improved). Larger numbers in the same abstract have a different character. In the power map of a low-power 64-bit CPU under a 2-nanometer design rule, the passage stating that the worst-case values for dynamic voltage drop—which occurs when circuits busily turn on and off—and static voltage drop—caused by average current—will be 82% and 96% smaller, respectively, is a prediction, not a measurement. What it was compared against is written only as "a baseline configuration" (DOI: 10.1109/ted.2022.3205561, devices are fabricated and measured, voltage drops are predicted).

The gains do not come in electricity alone. Standard cells are small basic circuits laid out like blocks in chip design, and their height is counted by the width corresponding to how many lines of wiring can pass through. The width of one such line is a track. If the power lines are on the front, it is 6 tracks; if buried, 5 tracks; and if moved to the back, 4 tracks. These numbers are what a comparative study wrote in the background of its abstract (DOI: 10.1109/islped58423.2023.10244504).

What that study calculated directly starts from the fact that as the cells become lower, the width of the nanosheets in the gate-all-around structure can also be reduced. Gate-all-around is a structure where the gate surrounds the channel from all four sides, and nanosheets are the thin plates that make up that channel (A Transistor Is a Switch). As the width was reduced, the gate capacitance—which is the amount of electricity that must be filled every time the gate opens and closes—decreased by 26% and 40%, respectively. Internal cell power improved by over 33% and 40%, and total chip power dropped by over 24% and 30%. The placement area decreased by 7% compared to the front side, and by an additional 17% from there when going all the way to the back side (DOI: 10.1109/islped58423.2023.10244504, design study. "3nm" is only in the title, and the abstract does not specify the node).

What changes bring about those gains needs to be looked at separately. In calculations adjusted to match 3-nanometer standard cells to a 5-nanometer actual chip, for the same area, cells with buried power lines showed reductions in delay (the time it takes for a signal to pass through a cell), transition time (the time it takes for the output to change), internal power, and pin capacitance (DOI: 10.1109/ted.2021.3138865, adjusted calculation). There are separate cases where internal power increases. That is when the number of channels is increased in nanosheet cells to further reduce delay. What increases power in this case is the number of channels, not the burying of power lines (what was reduced in the previous paragraph was the width of the nanosheets).

The conclusion of this calculation leans toward fin-based cells. The energy-delay product is the value obtained by multiplying the energy required for a single operation by the time taken, and the smaller it is, the more efficient the cell. The energy-delay product of fin-based cells with buried power lines was 12% smaller than the same cells without buried lines, and 10% smaller than nanosheet cells with buried power lines (DOI: 10.1109/ted.2021.3138865).

There is also a benchmark that ran physical design on an Arm Cortex-A53 up to imec's 3-nanometer-class process rules, comparing the front-side, buried, and backside configurations in sequence (DOI: 10.1109/ted.2022.3186657, physical design flow benchmark). When only the power lines were buried in the front-side power grid, the on-chip voltage drop decreased by 25% and off-chip voltage fluctuation by 17%. The guardband voltage—which is the extra voltage added in advance to prevent circuit errors even if the voltage fluctuates—decreased by 21%. When the power grid itself was moved to the back side, those same three values became 85%, 30%, and 60%. However, what baseline these percentages were measured against is not written in the abstract.

What the Front Side Was Also Doing

The backside can be used for signal wiring as well. One study targeting the 2nm node actually built through-nanosheets connecting the front and back, and measured a resistance of about 20 ohms and a capacitance (the ability to hold electricity) of about 0.04 femtofarads (DOI: 10.1109/iedm19574.2021.9720528, fabrication and measurement of through-nanosheets). In a design evaluation from the same study, moving long wires to the backside in a large block of SRAM improved performance and power efficiency by up to 44% and 32% compared to the front side. In logic cells driving long wires, speed increased by up to 2.5 times and energy efficiency by 60% (DOI: 10.1109/iedm19574.2021.9720528, evaluation values for the 2nm design).

The stacked structure of one NAND manufacturer routes signals using a single layer of aluminum wiring on the backside of the memory cell wafer. Electromigration is a failure where metal atoms are pushed away by stress, causing the line to break. The effect of the silicon substrate on this backside wiring's electromigration was addressed through both experiments and numerical analysis (DOI: 10.1109/irps48203.2023.10117817, experiments and simulation).

The front-side power grid was not just carrying electricity. A 2026 preprint that proposes a framework for jointly optimizing clock and signal wiring, assuming a backside power grid, accounts for that space. The wiring resources created on the backside are finite and must be shared between the clock and signals, and as the front-side power-ground shielding disappears, signal integrity—that is, the degree to which a signal arrives in its original shape without being distorted—gets severely worse. The thick power and ground lines on the front side had been standing between the signal lines to prevent interference all along. However, this preprint reports that it mitigates that problem. It utilized backside wiring in reverse to reduce coupling noise and crosstalk (signals from a neighboring line bleeding in), and improved timing, frequency, and signal integrity without adding extra shielding (arXiv:2607.13700v1, preprint, no numerical values in the abstract).

There are also studies that take a more direct aim. This is a 3D-TCAD simulation comparing three connection methods touching the backside power grid under area-matched conditions, in a next-generation structure where n-type and p-type transistors carrying electricity of different types are stacked vertically (DOI: 10.1109/ted.2025.3608778, 3D-TCAD simulation). The first is a pillar-like long through-via, the second is a line-shaped through-via, and the third is a method connecting the front and back via power tap cells, which are small cells responsible only for front-side metal lines and front-back connections. In this simulation, the third method was better. At the same power, the frequency was 2.2% higher than with the long through-via, and at the same frequency, the power was 4.7% lower. Even when cell height was reduced, the third method maintained its performance, whereas the long through-via side worsened due to increased resistance and unwanted parasitic capacitance. It was also possible to reduce the area by 12% without sacrificing frequency.

Just because the title is "Superiority of Front-side Connections" does not mean we should return power to the front side. The power grid remains on the backside, and this is a contest between whether to drill paths connecting the front and back as thick vertical pillars or to route them through front-side metals. Conditions are attached even to the ranges where that superiority stands out well. The gate pitch, which is the interval from one transistor's gate to the next transistor's gate ("What Is "3 Nanometers" the Length Of?"), must be in the range of 12 to 71 for there to be enough room to squeeze in power tap cells.

What Was Ground Away Was a Heat Spreader

In 2014, a team embedded heaters and temperature sensors into a 65-nanometer system chip (a chip containing multiple functions) and placed memory on top of it. They compared the test chip's measurements and simulations, and separately explored the effect of die thickness using exploratory thermal simulations. A die is a single piece of chip cut from a wafer. The conclusion is as follows: A die ground thin to use through-silicon vias may have a reduced ability to spread heat laterally, which can worsen hot spots, whereas a stacked die that is not ground thin can act as a heat spreader to ease the problem (DOI: 10.1109/icecs.2014.7050086, test chip measurements and simulations, with thickness effects via exploratory simulation). A heat spreader is a plate that spreads heat widely sideways so that it does not concentrate at a single point.

Wafer thinning is the process of grinding away precisely that plate. Circuits exist only in the thin topmost layer of the wafer, and the rest is the silicon supporting it. To route wiring from the back, almost all of that silicon must be shaved away.

Thermal resistance is a value representing how much a given layer dislikes releasing heat outward. At the same thickness, a cotton quilt has high thermal resistance and an aluminum plate has low thermal resistance. For heat to escape from inside a chip, it must pass through multiple layers in sequence, and the thermal resistances of those layers add up in turn. Self-heating is when a transistor heats itself up due to the current it flows. It differs from being heated along with the surroundings because a neighboring circuit is hot, and therefore the countermeasures are also different. Cooling the chip as a whole and where a single device discards its heat are separate problems.

The invited lecture summary mentioned earlier notes this from both sides, with the helpful side first. Moving to the back side lowers the thermal resistance of the remaining front-side wiring layers and allows the back-side metal layer to spread heat better laterally, meaning backside power delivery could help with some thermal issues. It then pivots with a "however." The silicon substrate beneath the transistors has traditionally acted as an effective heat spreader, and the self-heating resulting from grinding it away extremely or eliminating it altogether is the core concern (DOI: 10.1149/ma2026-01221255mtgabs, invited lecture summary, author's phrasing is "may").

The front-side wiring layers are also not an easy path for heat to travel through. There is an analytical model that estimates the thermal resistance in the direction of vertically piercing through layers, assuming wiring built by stacking 12 layers with an 18-nanometer metal pitch (the spacing between metal lines). That value is calculated as a function of how densely the metal lines and vias (short vertical connections linking layers) are packed, and how well the insulator filling the spaces between them conducts heat. The material properties of the insulator and the via connection configuration in this model were experimentally validated using test chips fabricated by a foundry (DOI: 10.1109/ectc51529.2024.00084, model + experimental validation).

The places where heat gets blocked are not limited to silicon alone. In a package model where a logic chip and HBM are placed side by side on an interposer, there is a modeling study that pinpoints silicon dioxide bonding layers with low thermal conductivity as the thermal bottleneck of the backside power delivery structure. HBM is memory used attached right next to the computing chip ("Fetching Is Slower Than Computing"). This study reports that incorporating dual-side cooling—which cools simultaneously using jets spraying coolant directly onto the chip from above and microchannels, which are very narrow water channels below—can lower the peak temperature of the logic chip by 22% (DOI: 10.1109/itherm55375.2024.10709471, modeling comparison).

There is a paper that teaches how to read temperature numbers. This is a 2025 simulation study that solved the heat of nanosheet devices and vertically stacked n-type/p-type devices using thermal SPICE, linked it with finite element analysis, and calculated everything in a single line from the transistor to the package (DOI: 10.1109/iedm50572.2025.11353735, thermal SPICE and finite element analysis). This paper nails down the $\Delta T$ it uses. $\Delta T$ (Delta T) is the peak temperature of the chip minus the ambient temperature, in other words, how much hotter it has become than the surroundings.

On that scale, transistor self-heating adds 2 to 9 degrees to $\Delta T$. A single hot spot accounts for 27 to 53% of the maximum $\Delta T$. Vertically stacked device structures have a maximum $\Delta T$ 27 to 25% higher than side-by-side structures. Four mitigation measures are adding dummy vias that do not carry electricity to the wiring layers, aluminum nitride bonding oxide, thermal-only vias, and high-thermal-conductivity insulators within backside power delivery, and they reduce the maximum $\Delta T$ by 5%, 5%, 7%, and 23%, respectively (DOI: 10.1109/iedm50572.2025.11353735).

40 Percent and 2 Degrees — Not Measured with the Same Ruler

The temperature numbers in this article measure different things and cannot be lined up and compared. The rulers diverge in four ways. What is being measured (a point on the chip, the hottest spot, the overall chip peak, a single device). What it is compared against (front-side structure, planar chip, before adding cooling). Whether it is a percentage or degrees. If it is a percentage, what percentage of the temperature itself (Celsius or Kelvin), or what percentage of the temperature rise above ambient. Different baselines for Celsius, Kelvin, or rise produce different numbers for the exact same change, and measuring from a smaller starting point makes the percentage look larger.

When the layer differs, the ranking changes. The simulation in the introduction noted that the structure with backside contacts at the base of the transistor has the highest hotspot temperature. However, another paper looking at the heat of gate-all-around devices says the exact opposite. Among various backside structures, the backside contact structure better suppresses self-heating and parasitic components, whereas the structure placing through-silicon vias in the contact layer between the transistor and the wiring layer suffers significant performance degradation (DOI: 10.1109/ted.2025.3569614, SPICE-compatible dynamic thermal model). The two are not contradictory. The former is chip-level hotspot temperature, and the latter is self-heating at what its abstract explicitly calls the "device-circuit layer." Yet the two papers neither cite nor refute each other. This is the reconciliation we have read out at the respective layers they clarified.

There is a more important sentence in the same paper. It states that what governs the dynamic performance of a circuit is not self-heating but parasitic components, and that self-heating instead exacerbates degradation phenomena that slowly age the device, such as hot-carrier injection or bias temperature instability (DOI: 10.1109/ted.2025.3569614). At this model's layer, what self-heating eats away at is lifespan rather than speed, meaning.

What is assumed also changes the numbers. Measuring the thermal diffusion of the backside metal layer directly with a test chip embedding heaters and temperature sensors, placing the backside metal lines in the direction of the temperature gradient was more effective for thermal diffusion. The same study notes the following regarding the results of the package-level model. Because the thermal penalty metric of backside power delivery is heavily dictated by what power distribution is assumed, that assumption must be defined first for an accurate interpretation (DOI: 10.1109/ectc51529.2024.00166, test chip experiment and model). In other words, assumptions write the bill. In a small-unit-structure simulation from the same study, thermal performance improved when an insulator with high thermal conductivity and a high metal density were used together in the backside metal stack.

When conditions change, even the direction flips. In a simulation evaluating a 64-core system-on-chip set at 140 watts per square centimeter by varying the stacking structure and wiring layers, adding a power delivery network on the back side increased the peak temperature by 2 degrees on a planar chip, but decreased it by 2 degrees in a 3D structure with memory stacked on top of logic (DOI: 10.1109/isvlsi61997.2024.00018, simulation). The sign of the same technology flipped from a penalty in planar to a benefit in stacked. The abstract does not explain why this split happens. Therefore, one cannot state unconditionally with a single number like "backside power delivery heats the chip by X degrees." The same simulation also notes that the memory-on-logic structure has a peak temperature 5 degrees higher than the planar baseline, and stacking 3 layers raises it by 12 degrees, requiring a 33% boost in heat extraction efficiency.

Even within the same A14 node, different studies yield different numbers. In an evaluation comparing physical designs where the same design was implemented with front-side versus back-side power delivery, the local temperature of the CPU using backside power delivery could be about 40% higher than the front-side counterpart (DOI: 10.1109/iedm45625.2022.10019349, physical design-based evaluation). The abstract does not clarify whether this value is a ratio of the temperature itself or of the temperature rise. The benefits of the same evaluation must be read alongside this. At the same frequency, a planar chip using backside power delivery consumed 57% less power than a front-side planar chip, with an 8% reduction in area at comparable power and performance.

The same evaluation also shows a scene where electricity and heat point in opposite directions. In a configuration where one CPU is stacked on top of another with power supplied from the bottom and the cooler placed on top, the upper die experienced a 39% greater voltage drop, while the lower die had a 17% higher temperature. In this setup, the side farther from the power source lost out electrically, and the side farther from the cooler lost out thermally. The authors conclude that because the two metrics point in opposite directions, additional challenges may arise for the co-design and optimization of power integrity and thermal reliability (DOI: 10.1109/iedm45625.2022.10019349).

Listing the numbers in this section by their respective rulers yields the following: 40% is local temperature, 14% is hotspot temperature, 2 degrees is peak chip temperature, and 22% is peak logic temperature. What differs among nodes, power distributions, and thermal boundary conditions (how much cooling is applied from the outside) varies for each figure, and whether the metric is a ratio of the absolute temperature or the temperature rise is not standardized either. The table in the introduction already contained a similar warning. In the same simulation, the power via approach showed a hotspot temperature difference of only about 1% compared to the buried rail approach despite having a much thinner substrate (converted from comparison values in the same abstract), and the authors attribute this to the lateral contact structure and backside metal density (DOI: 10.1109/iedm50854.2024.10873426). Thickness alone does not determine heat.

Temperature circles back to voltage drop. A 2009 analysis solving electricity and heat together in a 3D stacked system notes that the effect of temperature on DC voltage drop cannot be ignored. The thermal conductivity of the thermal interface material (the material filling the gap between the chip and the cooler), bump density (the small metal protrusions connecting the chip to the substrate), the stacking order of the dies, and the power supply locations simultaneously alter the final voltage drop and hotspot temperature (DOI: 10.1109/epeps.2009.5338465, parametrized electro-thermal co-analysis). While this analysis did not calculate the loop itself, connecting it through the general principle that metals have higher resistance when hotter, the loop runs as follows: heat raises resistance, resistance increases voltage drop, and raising the voltage to compensate for the voltage drop generates more heat.

Grinding Down Already Expensive Wafers

Before being ground thin, the wafer is temporarily attached to a carrier plate. A 2013 paper summarizing thin wafer processing describes this temporary bonding step as follows: "By the time a wafer reaches the temporary bonding stage, it has already been through countless processes and thus holds significant value in itself." That plate, just before grinding, is an expensive item that has already gone through almost all of its processing. The tool introduced by this paper is an in-line infrared metrology system that measures adhesive thickness, uniformity, and bonding voids (gaps trapped in the bonding interface) all at once before grinding to determine pass or fail (DOI: 10.1109/3dic.2013.6702341, metrology equipment development).

Yield is where this gets caught. Yield is the ratio of actually sellable products out of the ones made (They Chose Not to Make It One Chip). If a defect occurs in that plate, the entire process effort put in until then is discarded together. The backside process must grind the material to an extreme thinness while maintaining a very uniform thickness. The 2020 process demonstration ground the wafer down to below a micrometer while keeping the difference between the thickest and thinnest spots across the entire wafer—namely, the total thickness variation—below 70 nanometers. It drilled through-silicon vias with a top surface size of 180×250 nanometers to connect the front and back, and measured up to 99% electrically good connections in the fabricated structure (DOI: 10.1109/ectc32862.2020.00020, process demonstration and measurement).

Alignment is another problem. While bonding the wafers, the placement of the patterns on the wafers twists slightly, making the alignment requirements for the backside pattern harsh. A 2024 manufacturing demonstration answered by easing those requirements. Using long slit-shaped nano-through-silicon vias that self-align onto buried rails via front-side lithography creates margin for backside alignment. To this, they applied a thinning sequence that stops precisely at a 10-nanometer-thick silicon-germanium etch-stop layer pre-buried as the stopping point while grinding, and demonstrated for the first time nano-through-silicon vias filled with molybdenum without a barrier (DOI: 10.1109/ted.2024.3487080, manufacturing demonstration).

There are also three difficulties when grinding the copper on the back of the thin wafer using chemical-mechanical polishing. Chemical-mechanical polishing is a process that flattens a surface by rubbing it with a pad while flowing a chemical-mixed polishing slurry ("Nothing In Between"). First, the adhesive releases gas and deforms, increasing thickness variation and leaving residue inside the die. Second, because low pressure is applied for fear of breaking the wafer, residue remains at the edges. Third, copper remains in the depressions of the grinding marks. The same paper also offers three solutions. They are using thermosetting adhesive instead of thermoplastic, polishing longer with a polishing slurry that quickly cuts copper at low pressure while avoiding corrosion, and using a polishing slurry with strong surface protection for the depressions (DOI: 10.1109/3dic.2013.6702335, process development).

Whether transistors can withstand it is answered by one FinFET fabrication study we saw earlier. When additional heat treatment was applied after backside processing to recover threshold voltage and so on, the on and off current characteristics were similar or even better, and depending on the heat treatment choice, the on current was up to 8% and 15% higher (DOI: 10.1109/ted.2022.3205561).

What remains are faults that take time to reveal themselves. Electromigration is a phenomenon where electric current flows for a long time and pushes away metal atoms, causing wires to break. A simulation study treating electromigration as an electro-thermal-stress coupled model compares three backside structures for tungsten, ruthenium, and molybdenum to predict time-to-failure at the 2-nanometer node. Although it is a simulation, the authors note that failure locations and resistance degradation matched experiments well across several metals (DOI: 10.1109/iedm45741.2023.10413884, coupled simulation and comparison with experiment).

In the 108- and 124-megabit SRAMs using backside power delivery on the Intel 4 process, there is silicon data from mass-production lines, and the heaviest sentence in this paper is not a performance figure. The authors report that mass-production silicon data confirms there are no unique yield failure modes or performance failure modes caused by PowerVia (DOI: 10.1109/isscc49657.2024.10454501, 대량생산 실리콘 데이터). Compared to the baseline design, the minimum operating voltage was equal or better, performance was improved, and the bit density was 2% higher in one array of high-current SRAM. The frequently cited "approximately 6% performance improvement and approximately 30% voltage drop reduction" from the same abstract are values from another presentation cited as a reference by this paper, not measured values from this SRAM. The authors also note that SRAM has unique trade-offs distinct from logic, requiring separate designs for bitcells and peripheral circuits.

Putting Cooling Inside the Chip Makes the Wafer Thicker

If the path for heat to escape is blocked, the natural idea is to bring cooling water straight inside the chip. A 2011 paper that actually built and tested that idea described the technology of the time like this: "Current liquid cooling technologies inevitably increase the wafer thickness, which is contrary to the trend of through-silicon via technology." The authors made a heatsink that did not harm the performance of through-silicon vias, ran thermal tests compared with air cooling, and also reported the effect of its shape on the capacitance of the through-silicon vias (DOI: 10.1109/ectc.2011.5898797, design, fabrication, and thermal tests).

Here, the demands of electricity and cooling collide head-on. To route electricity to the back, the wafer must be thin; to bring water in, it must be thick.

There are also cooling designs aimed at backside power delivery. The title itself is a mitigation strategy, and the problem set up by the authors is that the thermal resistance between the CPU's power grid and forced cooling above the chip has greatly increased. The authors' answer is dual-side cooling that combines microchannels inside the wiring layer—inspired by the wiring layer resembling a three-dimensional microchannel cooler—with jets above the chip. Finite element analysis results show that when water at 283 kelvins (the temperature of cold water written on the absolute temperature scale) at 0.06 meters per second is introduced, the peak temperature drops by more than 20%, or about 20 degrees. This was the same whether the heat was generated uniformly or according to an actual power map. The price for that is an inlet pressure of 2,581 pascals required to push the water in (DOI: 10.1109/ectc51529.2024.00241, finite element analysis). This is a rare case that lists both 20% and 20 degrees together.

Sometimes the goal is not to let heat flow, but to block it. When stacking a hot processor layer and a temperature-sensitive low-power layer together, the design puts microfluidic cooling in the processor layer and thermal insulation with air or vacuum cavities in the low-power layer. In thermal modeling, when the power density of the processor layer is raised from 50 watts to 100 watts per square centimeter, the temperature rise of the low-power layer is 4 degrees with thermal insulation and 22 degrees without it (DOI: 10.1109/3dic.2013.6702398, thermal modeling. Through-silicon vias with an aspect ratio of 23 to 1 were actually fabricated).

There are also designs that try to solve electricity and heat in a single channel. This is a structure where the liquid flowing between layers serves as both coolant and power generator. Calculated with a design framework and model, compared to the state-of-the-art design techniques at the time of that research, it improves the voltage drop by up to 53% and 30% (for 60-watt and 190-watt dies, respectively) while keeping the peak temperature below 52 degrees, and uses no additional through-silicon via area. The same paper adds a qualifier. If there is a hot spot, the extent of that voltage drop improvement shrinks by up to 21% relative to the average (DOI: 10.1109/islped.2019.8824895, design framework and model).

Dedicated through-silicon vias that carry only heat look simpler, but finite element analysis lowers expectations. A grid of vias covering the entire chip lowered the average temperature only slightly, and near hot spots, the effect depended not just on the density but on how they were arranged (DOI: 10.1109/dsd.2011.70, finite element analysis).

Because most of the cooling methods in this section are models or laboratory prototypes, we cannot say based on this evidence alone that they are used in real chips.

Determining the Size of the Bill

We return to that table from the introduction. Among the five rows, the row where electricity flowed best was the hottest row, and the conclusion the authors drew from it was not pointing out a winner. What this simulation study actually delivers is that depending on the methodology that optimizes design and process together, they traded off which power delivery technology and resources to choose and how to allocate the CPU's power integrity budget (DOI: 10.1109/iedm50854.2024.10873426). Power integrity is the degree to which voltage is supplied properly without fluctuations.

The conclusion of another study that looked at self-heating in SRAM blocks beyond 3 nanometers takes the same shape. Calculated with a thermal RC network model, performance, stability, and area are all better compared to implementing the same design with traditional backside power delivery. However, the authors immediately add below that because of its unique structural characteristics, the co-design and optimization of circuit performance and thermal reliability create additional challenges (DOI: 10.1109/irps48228.2024.10529350, thermal RC network model).

The point where heat blocks performance even has a name. It is a concept brought out by a preprint that managed the performance, energy, and temperature of three-dimensional processor-memory stacking together, rather than backside power delivery. Effective thermal capacity is the amount of heat generation beyond which performance no longer increases even if voltage and frequency are raised further. Their controller improved the energy-delay squared product (an efficiency metric that weighs speed more heavily) by up to 30% compared to a fixed frequency in a simulator and lowered core temperatures by up to 8 kelvins. At the same energy efficiency as Linux's on-demand method, which raises and lowers clocks depending on the load, it lowered temperature by 6 kelvins, increasing lifespan reliability by up to 59% (arXiv:1808.09087v2, preprint/simulator-based).

So the answer these pieces of evidence point to is the bill. Routing electricity to the back reduces voltage drop, clears the front, and lowers the cell height. Although mostly simulations, multiple studies point in the same direction through different methods. And that price is billed in three places. The price billed in heat is because the silicon ground away was a heat spreader. The price billed in process is because an already expensive wafer must be polished evenly. The price billed in reliability is because one thermal model study reported that self-heating mainly worsens device aging rather than speed, and the SRAM study cited the co-design of performance and thermal reliability as an additional challenge.

The size of the bill is determined by the conditions. In one simulation, depending on whether it is a planar chip or a stacked chip, the same technology raises the temperature by 2 degrees in some cases and lowers it by 2 degrees in others. What is assumed for the power distribution heavily dictates the thermal penalty metric. There are structures where even though the substrate is much thinner, the hot spots are hardly any hotter. In a simulation comparing matched areas, taking the path around the front metal was better than thick vertical pillars, and that superiority also comes with conditions spanning a few gate pitches.

The unit of performance has dropped down yet another layer. In the past, performance was how small transistors could be made, and after that, performance was how pieces were attached and what they were placed upon. Now, the path through which electricity travels down inside the chip and the path through which heat escapes are performance. Those two paths pass through the same silicon, so widening one narrows the other.

Source Papers

• "Power and Thermal Integrity of Backside Power Delivery Networks in Sub-2nm CPUs" (2024) — DOI: 10.1109/iedm50854.2024.10873426 — Design and evaluation simulation. Direct backside contact reduces IR drop by 91.3% (relative to the front side, at operating temperature) while peak hotspot temperature is 14% higher. The conclusion is that it is a trade-off methodology rather than a winner.
• "System-Level IR Drop Impact of RISC-V SoCs" (2022) — DOI: 10.1109/impact56280.2022.9966707 — Characterization and modeling. A 100 mV drop degrades 500 MHz and 1 GHz CPUs by up to 50%. Package, board, and VRM account for up to a 5.8% increase.
• "Electrical and Fluidic C4 Connections for Interlayer Liquid Cooling in 3D ICs" (2010) — DOI: 10.1109/ectc.2010.5490755 — Wafer-level fabrication and fluid sealing. 100 W/cm² and over 100 A were projections at the time.
• "Advanced Logic Scaling in the Angstrom Era" (2026) — DOI: 10.1149/ma2026-01221255mtgabs — Invited talk summary. The silicon substrate has historically been an effective heat spreader, and extreme thinning of it is a key concern. However, BSPDN may also help with heat.
• "Buried Power Rails and Nano-TSVs" (2022) — DOI: 10.1109/ectc51906.2022.00244 — Fabrication and measurement. Final silicon thinning to under 500 nm, backside alignment within 10 nm. Resistance characterized for W, Co, and Ru, with measurements matching simulations.
• "FinFETs Connected to Buried Power Rails from Both Wafer Sides" (2022) — DOI: 10.1109/ted.2022.3205561 — Devices fabricated and measured. The 82% and 96% reductions in IR drop are predictions, and the baseline configuration is not in the abstract. Ion increases by up to 8% and 15% after backside processing.
• "Comparison of Front-Side, Buried, and Backside Power Rail Structures" (2023) — DOI: 10.1109/islped58423.2023.10244504 — Design study. Cell heights of 6 to 5 to 4 tracks are background sentences in the abstract. What was measured is a 26% and 40% reduction in gate capacitance, a 24% and 30% reduction in chip-wide power, and a 7% reduction in floorplan plus an additional 17% reduction. ⚠️ "3nm" appears only in the title.
• "PPA of Sub-3nm Standard Cells Using Buried Power Rails" (2022) — DOI: 10.1109/ted.2021.3138865 — Calibrated calculations. Burying them reduces delay, transition time, internal power, and pin capacitance. Internal power increases when the number of nanosheet channels is increased. The EDP of pin-based cells is 12% smaller than unburied cells of the same type and 10% smaller than buried-rail nanosheet cells.
• "Comprehensive Evaluation of Buried Power Rails and Backside Power Delivery for Sub-5nm Nodes" (2022) — DOI: 10.1109/ted.2022.3186657 — Arm Cortex-A53 physical design benchmark. Front-side plus buried yields 25%, 17%, and 21%; backside grid yields 85%, 30%, and 60%. The baseline is not in the abstract.
• "SRAM Macros and Logic Using Backside Routing at 2nm" (2021) — DOI: 10.1109/iedm19574.2021.9720528 — nTSV fabrication and measurement (approx. 20 Ω, approx. 0.04 fF). Moving the backside to signals. SRAM up to 44% and 32%, long routing logic cell speed up to 2.5x.
• "Electromigration in Xtacking Aluminum Backside Interconnects" (2023) — DOI: 10.1109/irps48203.2023.10117817 — Experiments and numerical analysis. The NAND stacked structure routes signals to the cell wafer backside Al layer. Positive correlation between hydrostatic stress and the SM index.
• "CSCO — Clock and Signal Co-Optimization Considering Backside Power Networks" (2026) — arXiv:2607.13700v1 (preprint) — Backside resources are finite, causing clocks and signals to compete, and the loss of front-side power-ground shielding degrades signal integrity. However, this paper's answer is to mitigate coupling noise and crosstalk using backside routing, reporting improvements without adding shielding. No numerical values in the abstract.
• "CFET Backside Power Network Connection Area Trade-Off Comparison — Front-Side Connection Advantage" (2025) — DOI: 10.1109/ted.2025.3608778 — 3D-TCAD. Front-side metal plus power tab cells yield +2.2% frequency, −4.7% power, and 12% less area compared to pillar vias. The power network remains on the backside, with the sweet zone at 12 to 71 gate pitches.
• "Thermal Impact of 3D Integration and Die Thickness" (2014) — DOI: 10.1109/icecs.2014.7050086 — Measurement and simulation comparison of two 65 nm SoC test chips with embedded heaters and sensors (with and without stacked memory). Die thickness is used only for exploratory thermal simulations: thinned dies can worsen hotspots, while unthinned dies can help as heat spreaders.
• "Experimentally Validated Thermal Modeling Predictions of BEOL and BSPDN Stacks" (2024) — DOI: 10.1109/ectc51529.2024.00084 — Model plus foundry test vehicle validation. Out-of-plane thermal resistance of 12-layer interconnects with an 18 nm pitch is estimated as a function of metal and via density.
• "Double-Sided Cooling Analysis of Backside Power Delivery Networks on 2.5D Packages" (2024) — DOI: 10.1109/itherm55375.2024.10709471 — Modeling comparison. Identifies the low thermal conductivity SiO₂ bonding layer as the thermal bottleneck. Double-sided cooling reduces peak logic temperature by 22%.
• "Transistor-Package Thermal Simulation and Hotspot Mitigation" (2025) — DOI: 10.1109/iedm50572.2025.11353735 — Thermal SPICE plus finite element. The only paper in this set that explicitly specifies ΔT (= peak temperature − ambient temperature). Self-heating is 2 to 9 degrees, hotspots are up to 27% to 53% of ΔT, and four mitigation measures yield 5%, 5%, 7%, and 23%.
• "Thermal Impact of Backside Power Networks in GAAFET Technology" (2025) — DOI: 10.1109/ted.2025.3569614 — SPICE-compatible dynamic thermal model. At the device-circuit level, backside contacts better suppress self-heating and parasitics. Dynamic performance is dominated by parasitics, and self-heating worsens HCI and BTI.
• "Block-Level and Package-Level Thermal Evaluation of Backside Power Networks" (2024) — DOI: 10.1109/ectc51529.2024.00166 — Heater-sensor test chip experiments and models. Orienting backside metal lines in the direction of the temperature gradient. Power distribution assumptions heavily dictate the thermal penalty metric. In unit cells, improvements are achieved through a combination of high thermal conductivity dielectric and high metal density.
• "3D Integration and BEOL Thermal Analysis of Many-Core SoCs" (2024) — DOI: 10.1109/isvlsi61997.2024.00018 — Simulation (64 cores, 140 W/cm², A14). Rear PDN adds +2 degrees in 2D and −2 degrees in 3D memory-on-logic. MoL adds +5 degrees compared to 2D, and 3 tiers add +12 degrees.
• "PPA and Thermal Analysis of A14 Backside Power Network 2D and 3D ICs" (2022) — DOI: 10.1109/iedm45625.2022.10019349 — Physical design-based evaluation. 57% lower power and 8% smaller area in 2D at the same frequency. Local temperatures can be roughly 40% higher than the front side (absolute values or increments not specified). In CPU-on-CPU, the upper die IR drop increases by 39% and the lower die temperature by 17% — additional challenges may arise in co-design (author wording).
• "Component Effects on 3D System Integration Power Distribution Networks" (2009) — DOI: 10.1109/epeps.2009.5338465 — Electro-thermal co-analysis. The effect of temperature on DC IR drop is negligible. TIM, C4 density, stacking order, and power supply locations alter both together.
• "Recent Advances in Thin Wafer Processing" (2013) — DOI: 10.1109/3dic.2013.6702341 — Metrology equipment development. Wafers at the temporary bonding stage already hold considerable value. Therefore, infrared inline metrology is introduced to measure adhesive thickness, uniformity, and voids before grinding.
• "Extreme Wafer Thinning and Nano-TSV Processes" (2020) — DOI: 10.1109/ectc32862.2020.00020 — Process demonstration and measurement. Total thickness variation under 70 nm, top CD 180×250 nm nTSVs, and up to 99% electrically sound connections.
• "Backside Power Delivery with Mo-Filled Slit Nano-TSVs Relaxing Backside Alignment" (2024) — DOI: 10.1109/ted.2024.3487080 — Fabrication demonstration. Self-aligned slit nTSVs ease the stringent backside alignment requirements caused by lattice distortion during bonding. Features a 10 nm SiGe etch stop layer and barrier-free Mo filling.
• "Copper CMP Challenges for Backside TSVs and RDLs on Thin Wafers" (2013) — DOI: 10.1109/3dic.2013.6702335 — Process development. Three residue issues (total thickness variation, edge, and grinding marks) and their respective solutions (thermosetting adhesive, low pressure plus overpolishing, high-passivation slurry).
• "Electromigration in N2 Backside Power Networks — Performance, Area, and Reliability Trade-Offs" (2023) — DOI: 10.1109/iedm45741.2023.10413884 — Electro-thermal-stress coupled simulation. Compares BPR, TSVM, and BSC across W, Ru, and Mo. The authors note that failure locations and resistance degradation match experiments well across multiple metals.
• "Intel 4 SRAM Design Using PowerVia" (2024) — DOI: 10.1109/isscc49657.2024.10454501 — Mass-production silicon data. No intrinsic yield or performance failure modes due to PowerVia. VMIN is equal or better, performance is improved, and bit density is up by 2%. ⚠️ "Performance ≈6%, IR drop ≈30%" are values from another presentation cited by this paper.
• "Electro-Thermal Co-Design of 3D IC Microfluidic Heat Sinks" (2011) — DOI: 10.1109/ectc.2011.5898797 — Design, fabrication, and thermal testing. Current liquid cooling inevitably increases wafer thickness, which runs counter to the trend in TSV technology.
• "Thermal Mitigation Strategies for Backside Power Delivery Networks" (2024) — DOI: 10.1109/ectc51529.2024.00241 — Finite element analysis. The problem is increased thermal resistance between the power grid and forced cooling, and the answer is double-sided cooling with microchannels in the BEOL and jets above the chip. Peak temperature drops by over 20% or about 20 degrees, at the cost of an inlet pressure of 2581 Pa.
• "Intra-Tier Cooling and Thermal Isolation Techniques for Heterogeneous 3D ICs" (2013) — DOI: 10.1109/3dic.2013.6702398 — Thermal modeling (23:1 TSVs fabricated). When the processor tier goes from 50 to 100 W/cm², the low-power tier temperature rise is 4 degrees with insulation and 22 degrees without it.
• "Thermally-Aware Power Network Design for 3D MPSoCs Using Flow-Cell Arrays" (2019) — DOI: 10.1109/islped.2019.8824895 — Design framework and model. Interlayer liquid serves dual roles for cooling and power generation. Compared to state-of-the-art techniques, IR drop is reduced by up to 53% and 30%, and peak temperature remains below 52 degrees. When hotspots are present, the improvement shrinks by up to 21% relative to the average.
• "Thermal Effects of TSVs in 3D Die-Stacked ICs" (2011) — DOI: 10.1109/dsd.2011.70 — Finite element analysis. A chip-wide TSV lattice drops average temperatures only slightly, and local effects depend on layout arrangement as well as density.
• "Self-Heating Effects in Sub-3nm Backside Power Network Device-Circuits" (2024) — DOI: 10.1109/irps48228.2024.10529350 — Thermal RC network model. Better performance, stability, and area than front-side PDNs of the same design. However, structural traits create additional challenges for co-designing performance and thermal reliability.
• "TRINITY — Performance, Energy, and Thermal Management of 3D Processor-Memory Stacks" (2018) — arXiv:1808.09087v2 (preprint) — Simulator-based. "Effective thermal capacitance" refers to the heat dissipation level beyond which raising voltage and frequency yields no further performance gain. Compared to a fixed frequency, ED²P increases by up to 30%, core temperature drops by up to 8 K, and compared to an on-demand governor, it drops by 6 K with up to a 59% increase in lifetime reliability.