2D Semiconductors — Graphene's Betrayal and the Real Candidate for the "Post-Silicon" Era

Off and Still One-Fifth

A 2010 paper described the state of graphene transistors like this: a graphene transistor with a gate placed on top of the channel does not turn off properly, and the ratio of the current when turned on to when turned off is roughly 5. That was the situation at the time that paper stood upon (arXiv:1001.3915).

A transistor is a tiny switch turned on and off by electricity. A gate is placed over the channel—the path where current flows—with a thin film in between, and the channel is opened and closed by the voltage applied to the gate ("A Transistor Is a Switch — A Tiny Faucet You Open and Close with Electricity"). The material of the channel is a semiconductor, which lets electricity flow or blocks it depending on the conditions—namely, silicon. Graphene is a two-dimensional crystal made of a single layer of carbon atoms. This material once gathered great expectations as a material to make channels instead of silicon.

The on/off ratio is the value obtained by dividing the current flowing when the transistor is turned on by the current flowing when it is turned off. In terms of the faucet from "A Transistor Is a Switch", it is the ratio of the water stream when opened wide to the leaking water stream when tightly closed. If this value is 5, it means that even when closed, one-fifth of the stream from when it was turned on continues to flow.

The reason had been known early on. Graphene has no bandgap. A bandgap is an energy range inside a material where electrons cannot stay at all. Electrons below this range cannot go up unless they receive the energy to leap across the range all at once, and if they cannot go up, current does not flow. Turning off a transistor is the act of making electrons stand in front of this empty range. Graphene has no range to make them stand.

So the authors of this paper attached gates above and below a bilayer where two sheets of graphene are stacked, and applied an electric field perpendicular to the layers. The result was an on/off ratio of roughly 100 at room temperature, and roughly 2,000 at 20 K (Kelvin, a very low temperature). The bandgap measured by current was greater than 130 meV (millielectronvolts) when the strength of the electric field applied to the layers (the average electric displacement) was 2.2 V/nm, and 80 meV at 1.3 V/nm. The authors concluded that this shows the great potential of bilayer graphene in digital electronics, terahertz technology, infrared nano-optics, and more (arXiv:1001.3915, measured).

A room-temperature value of 100 is twenty times better than 5. Yet transistors made of atomic-thickness semiconductors that possessed a bandgap from the beginning have reported values for the same-named indicator ranging from $10^6$ to over $10^9$ (arXiv:1512.05016, arXiv:2312.04849). Because the device structures, materials, and measurement conditions all differ, these are not values measured with the same ruler. Still, the number of digits is different. This article follows where graphene, which emerged as a "miracle material," got stuck as a channel for digital transistors, and examines the rivers that atomic-thickness semiconductor candidates must cross.

All articles cited in this article are open access copies uploaded to arXiv, mixing those that have passed through societies and journals with preprints before peer review. Because values measured by experiment, values extracted by calculation, and the current status organized by reviews are also mixed, which one applies is written in parentheses for each citation. Because this is a fast-moving field, figures stating "the highest up to that time" are records from the year that paper came out.

Why Graphene?

What captured academia's attention about graphene was the speed at which electrons travel inside it. Mobility is a value representing how fast electricity-carrying particles move when pushed by an electric current of the same strength; the larger it is, the better current flows at the same voltage. In graphene samples suspended in the air so they didn't touch a substrate, electron mobility of up to 2×10⁵ cm²V⁻¹s⁻¹ was observed (arXiv:2010.10382, review). Although it was a value obtained from the top suspended sample, it was a figure with a larger digit than silicon.

The situation on the silicon side also raised expectations. A 2013 graphene electronic device review diagnoses that the speed of silicon transistors had hit a plateau during the preceding decade, with the main reasons being miniaturization techniques and the short-channel effect. The short-channel effect is a phenomenon where, as the channel becomes shorter, the gate fails to adequately control the channel. According to the same review, graphene—which is as thick as a single atom and conducts electricity well—seemed poised to alleviate some of the weaknesses of silicon transistors, and was counted among the most promising candidates to replace silicon in nano-sized transistors (arXiv:1309.0205, review). A 2020 review on graphene transistors also notes that as Moore's Law ("What Is "3 Nanometers" the Length Of? — Measuring a Chip's Name with a Tape Measure")—the observation that the number of transistors packed into a single chip doubles every fixed period—began to flatten out, the industry's need for "post-silicon" technology has become distinct (arXiv:2010.10382, review).

Graphene also opened the door to the entire family of atomic-thickness materials. Heterostructures are structures where different atomic-thickness crystals are stacked or joined side by side. Starting from graphene, the world of atomic-thickness materials has greatly expanded—including semiconducting atomic-thickness crystals, MXenes, and van der Waals heterostructures in which these are stacked layer by layer without chemical bonds (arXiv:2503.22476, roadmap).

A Switch That Is Hard to Turn Off — Reviews That Long Ago Marked Them as "Complements"

In 2009, when the graphene craze was in full swing, the review "Status of Graphene Transistors" defines graphene transistors from its very first sentence as a potential complement to CMOS, the standard technology for silicon chips. It did not write substitute. And it lists two things side by side. The fact that there is no bandgap becomes a serious flaw for logic circuits that make decisions by weaving together on and off. Conversely, graphene transistors are an object of interest in analog high-frequency applications. The same review also covers methods for creating gaps in graphene and new switching methods (arXiv:0911.4685, review). This is because high-frequency amplifiers do not require the clear on and off of logic circuits (arXiv:1309.0205, review).

The reason lies in graphene's energy structure. Among the energy ranges where electrons can stay, the zone above the bandgap is called the conduction band, and the zone below it is called the valence band. In graphene, these two bands meet at a single point called the Dirac point. Because graphene is a semimetal where the conduction band and valence band meet at the Dirac point, its bandgap is zero. A review on graphene transistors notes that this property—a zero bandgap—is a headache in the context of digital electronic applications (arXiv:2010.10382, review). The expression in that review, which diagnosed the speed stagnation, is even more direct. Graphene inherently lacks a gap (bandgap), but transistors require a bandgap that clearly distinguishes between on and off (arXiv:1309.0205, review).

The same wall was the starting point in the laboratory as well. Research aiming for ultra-high-performance devices by wrapping graphene with hBN (hexagonal boron nitride), an insulator two atoms thick, also begins with the sentence that the fact that there is no band gap at the Dirac point is a stumbling block to making this system a usable transistor. The solution was alignment. If the crystal directions of hBN and graphene are precisely matched, the pattern where the two crystals overlap (moiré) gives the electrons periodic energy undulations, and this moiré potential opens a gap at the Dirac point. By handling the two gates separately, such as matching the charge density of the channel with the bottom front gate and turning that channel off with the top local gate, they were able to match it to the optimal on/off region (arXiv:2405.06267, measured). Graphene before a gap is artificially opened is difficult to become a usable digital switch.

An evaluation in a 2012 study was even colder. It stated that while graphene was considered a strong candidate to succeed silicon, it had not actually demonstrated capabilities beyond standard semiconductor materials up to that point. The only usable graphene devices demonstrated at that time were practically micron-sized ultra-high-frequency analog transistors and quantum Hall devices for measurement. That does not mean the conclusion was pessimistic. Graphene cut to nano-sizes has rough edges that significantly degrade mobility, but growing graphene on a silicon carbide (SiC) surface with pre-etched structures made it possible to bypass this roughness and create high-quality ribbons and rings. The authors present this as a path for patterning graphene at the nano-scale (arXiv:1202.5975, measured).

Ways to Force Open a Gap, and the Second Wall

Researchers have tried several different paths to create and attach a gap where graphene has none. These include applying a vertical electric field to a bilayer, cutting it into narrow ribbons, or aligning it with a substrate to use a moiré potential (arXiv:2010.10382, arXiv:2405.06267). Another way is to insert heavy atoms. When tellurium was inserted into graphene grown on iridium, a gap of about 240 meV opened at room temperature in the band (the Dirac cone) around the Dirac point, and graphene's characteristic linear energy relationship remained intact. The authors consider this interpretation to be consistent with the spin-orbit coupling inherent to tellurium-grown graphene (arXiv:2311.16792, spectroscopic measurements on a metal substrate).

A gap can also open unintentionally. When bilayer graphene is laid under metal electrodes, charge transfers from the surface, creating a potential difference between the two layers and opening a gap in that spot. This gap has been pointed out as a cause of the resistance that builds up when current crosses from the electrode to the channel (arXiv:1412.1202, measurements).

Every path that opened a gap came with a price. One example is nanoribbon transistors where wafer-scale grown graphene was cut down to a width of 12 nm (nanometers). A wafer is a thin, round silicon plate used to make chips ("Lithography — Painting Circuits with a Brush of Light"). This graphene was grown to wafer scale using chemical vapor deposition (CVD), where gaseous raw materials are reacted on a substrate to grow a film, and the ribbons were cut by carving patterns with an electron beam. The bandgap of the ribbon was estimated to be about 0.1 eV (electron-volt), and the fact that the minimum current on the off-side varied greatly with temperature was also a sign that a gap had opened. However, the drain current modulation, which corresponds to the on/off ratio, was close to 10⁶ at 4 K, but about 10 at 300 K (room temperature) (arXiv:1204.0499, measurements). A gap had opened, but it was still not enough for a room-temperature switch. What the authors emphasized in these results is the progress in wafer-scale CVD graphene and the demonstration that a gap opens in nanoribbon transistors.

Nanoribbons are not a dead end. When a nanoribbon transistor with a width of about 10 nm was built on epitaxial graphene grown broadly with aligned directions on a crystal substrate, and a gate was placed on top, a gap of about 0.14 eV opened. The important part comes next. Unlike previous reports that current flows irregularly in nanoribbons and that rough edges significantly degrade performance, current in these devices flowed along the bands like a conventional semiconductor at room temperature, and showed tunneling—drilling straight through between bands—at low temperatures. The authors conclude that "carefully fabricated" narrow nanoribbons behave like conventional semiconductors and remain a candidate for electronic switching devices (arXiv:1310.6823, measurements + modeling). The weight of this conclusion is carried by the qualifier "carefully fabricated."

Following this clue all the way led to the bilayer graphene research in 2022. What this study dealt with was disorder. Disorder is a general term for things like impurities, defects, and rough interfaces in a sample that disrupt the even arrangement of a crystal, making the energy landscape where electrons pass rugged. The authors' diagnosis is this: the first evidence of a gap whose size can be changed with an electric field came out a decade ago, but it took that long to make a heterostructure clean enough to completely block current or trap charge with that electrically opened gap.

Bilayer graphene using graphite as a gate had extremely low disorder and practically no states trapped inside the gap, showing a cleanly tunable gap up to 120 meV. This was confirmed by current changes according to temperature and measurements scanning energy by applying voltage. The gap size matched theory well and could completely suppress the current (arXiv:2206.02057, measurements).

Graphene had two walls. One was that there is no gap, and the other was that even when you open a gap, the disorder of the sample fills that gap right back up. The second wall only retreated after lowering the disorder by changing gate materials and device technology. None of these—special substrate alignment, atom insertion, graphite gates, or ribbon widths around 10 nm—are technologies that can be directly transferred to silicon-style mass production.

An Atomically Thin Semiconductor with a Bandgap from the Start

Meanwhile, another candidate drew attention. It is a semiconductor that is atomic-scale in thickness and possesses a bandgap from the beginning. This is the group we passed by without a name earlier in 「Semiconducting Atomically Thin Crystals」.

Transition metal dichalcogenides (TMDs) are three-layer atomic-thickness crystals in which a single layer of metal atoms, such as molybdenum or tungsten, is sandwiched top and bottom by a single layer of atoms like sulfur or selenium. Representative examples are $MoS_2$ (molybdenum disulfide) and $WSe_2$ (tungsten diselenide).

A review summarizing TMD devices suggests that their two-dimensional structure matches a direct bandgap in the visible light region, which is well-suited for both emitting and absorbing light, making them fit for both digital electronics and optoelectronics. Yet what that review does is not declaring a winner. It places the performance of the devices side by side with competing technologies to weigh their advantages and drawbacks together, and sketches a roadmap for the future (arXiv:1402.0047, review). A review on contact and interface engineering also highlights three strengths of TMDs: high electron mobility, mechanical strength, and a tunable bandgap (arXiv:2601.02628, preprint·review).

The reason atomic thickness is advantageous lies in how strongly the gate grips the channel. The thinner the channel, the more powerfully the gate controls the entire channel, making it easier to suppress short-channel effects even when the channel becomes short. To evaluate this grip with numbers, two values are needed. Gate capacitance is a value representing how much charge the voltage applied to the gate gathers in the channel. Equivalent oxide thickness (EOT) is a value converting the gate insulating film into the thickness of a silicon oxide film that produces the same effect.

When the insulating film becomes as thin as a nanometer, the channel material itself has a limited capacity to accept charges, making the gate capacitance smaller than the value calculated solely from the insulating film (oxide capacitance). For an n-type channel of single-layer $MoS_2$ with a gate on only one side at an EOT of 0.5 nm—meaning a channel where electrons carry the current—the gate capacitance is limited to 63 to 78% of the oxide capacitance. This is the value when the gate voltage applied beyond the threshold voltage (overdrive voltage) is 0.5 to 1 V. The threshold voltage is the gate voltage at which a transistor starts to turn on (「Why Did the Clock Stop at 4 GHz — Dark Silicon and the Power Wall」).

After noting this limitation first, the authors calculated that in a device with gates on both the top and bottom sides, the on-state gate capacitance is 50% larger than that of silicon at the same 0.5 nm EOT, and more than three times that of InGaAs at a 1 nm EOT. The conclusion is that 2D semiconductors hold promise for nanodevices in future manufacturing generations (arXiv:2301.03453, calculation). This comparison is a calculated value derived under the conditions of an EOT of 0.5 nm and 1 nm.

The potential did not reside only in calculations. In 2016, a 1-bit microprocessor made solely from single-layer $MoS_2$ was demonstrated. It executed user programs stored in external memory, performed logic operations, and communicated with peripheral devices. Consisting of 115 transistors, it was the most complex circuit made of a 2D material up to that time, and the authors noted that this 1-bit design could be scaled directly to multiple bits (arXiv:1612.00965, measurement). TMDs actually began running logic circuits, something that had been difficult with graphene transistors. The 2D materials roadmap also lists 2D transistors as one of the breakthrough applications among core technologies (arXiv:2503.22476, roadmap).

The Seam Between Electrode and Channel — Contact Resistance Varies Across Literature

A wide river flows between the laboratory's single device and mass-produced chips, and one of its core bottlenecks is contact.

Contact resistance is the resistance that arises exclusively at the boundary when electric current crosses over from the metal electrode into the semiconductor channel. Using the faucet analogy from "A Transistor Is a Switch — A Tiny Faucet You Open and Close with Electricity", it is like a narrow seam connecting the incoming water pipe to the faucet. No matter how wide the water path is, if it gets blocked at the seam, only that limited amount flows. Contact resistance is written in ohm-micrometers ($\Omega\cdot\mu\text{m}$), meaning it is the resistance scaled to a contact with an electrode width of 1 micrometer.

When metal is attached to a 2D semiconductor, a Schottky barrier forms at the boundary—an energy hill that electrons must climb to go from the metal to the semiconductor, making it difficult for current to enter. The energy required to detach a single electron from the metal is called the work function, and according to the Schottky-Mott rule, one can choose metals with different work functions to adjust the height of this hill. Bulk semiconductors like silicon obtain low-resistance contacts by heavily doping impurities into the contact region instead of choosing metals (arXiv:2312.04849).

This adjustment does not work well at the boundary between metal and TMD. Fermi level pinning is a phenomenon where, even when the metal is changed, the barrier height at the boundary does not move sufficiently according to the metal's work function and remains stuck within a narrow range. Therefore, the barrier of a metal-2D TMD contact is difficult to predict with the Schottky-Mott rule, and that barrier leads to high contact resistance and insufficient current supply, hindering performance improvements in TMD transistors and integrated circuits (arXiv:2601.02628, preprint/review).

There is something to understand first in this field. The reported contact resistance numbers vary widely from one another. A 2017 study notes that the way charge enters from the metal into the TMD layer was still unclear at the time, and reported values for the Schottky height and contact resistance diverged significantly, especially in monolayers. The authors present four answers using monolayer MoS₂ devices attached with gold (Au) and nickel (Ni).

First, charges cross over two barriers sequentially, and their heights are determined by how strongly the metal and TMD are intertwined. Second, because that barrier is multi-dimensional, the conventional Richardson equation used to calculate current crossing the barrier is incorrect. Third, they propose a new method to filter out changes in channel resistance according to temperature and extract the barrier height. Fourth, they derive the Landauer limit, which is the theoretical floor down to which contact resistance can drop. Comparing that floor with actually achieved values concludes that there is still plenty of room for technical improvement (arXiv:1703.00671, theory+experiment).

There are also preprints that directly address why the literature diverges. Even how the electrical conductivity of MoS₂ changes depending on the number of layers was not settled, with reports of it increasing and reports of it decreasing coexisting. The authors measured MoS₂ thinly peeled (exfoliated) from a large crystal—placed on gold in ultra-high vacuum versus placed in air—side by side, reporting that, contrary to the dominant view in the literature, the pristine MoS₂/Au junction has very high conductivity and is ohmic. Ohmic means the property of a contact where current flows in proportion to voltage and is not blocked by a barrier. The authors attributed the cause of the high contact resistance reported so far to interface contamination, interpreting that the contamination even disturbed the layer-number dependency, creating discrepancies in the literature. Slightly contaminated contacts could revive their original ohmic contacts simply by applying localized force to press them back into close contact (arXiv:2605.27187, actual measurement+transport simulation).

What was being measured was also a problem. A 2021 study revealed points where the classical contact resistance model fails in 2D material contacts, fixing the model by adding a component called lateral quasi-junction resistance ($R_{\text{jun}}$). When this component was measured in monolayer MoS₂ devices attached with nickel, $R_{\text{jun}}$ was the dominant component of contact resistance in 2D devices that were not doped—a process of mixing other atoms to change the degree of electrical conduction. Changes according to the voltage of the gate placed under the channel (back gate) and temperature were also mostly created by this. The authors noted that this revised model helps understand state-of-the-art contact engineering techniques from the perspective of reducing $R_{\text{jun}}$ (arXiv:2110.02563, actual measurement+model).

There are also models that quantify the size of the wall. When a 3D metal is placed on a 2D semiconductor, current crowds into specific points, and this model separates that crowding from the contact's intrinsic resistance. Crowding can be reduced through doping and contact patterning, but the model concludes that gaps remaining at the interface ultimately limit the contact resistance. Charge-transfer doping is a method of filling the particles that carry electricity to the channel by allowing them to exchange charge with an adjacently attached material. Even when this doping is made heavy beyond $2\times 10^{13}\text{ cm}^{-2}$, the highest-level contact resistance at that point was about 100 times the ballistic limit. The ballistic limit is the floor value when assuming electrons pass through without colliding with anything. The target the authors present as an ideal value for extremely miniaturized devices is under $10\text{ }\Omega\cdot\mu\text{m}$ (arXiv:2105.10792, model+experimental data comparison).

Just how far have we actually come? A 2021 study statistically investigating contacts where gold was attached to CVD-grown monolayer MoS₂ using a transmission line structure reported a value as low as $330\text{ }\Omega\cdot\mu\text{m}$. A transmission line structure is a measurement method where devices with varying channel lengths are made side by side to measure and separate the contact share and the channel share. This figure is noted by the authors as the lowest among those reported up to that point. The same paper noted that the transmission line model partially deviates in short-channel devices with a gate placed under the channel, and discussed ways to revise the model (arXiv:2106.08673, actual measurement). As of 2021, the ruler used to measure the height of the wall still had parts left to fix.

Since $10\text{ }\Omega\cdot\mu\text{m}$ is a target suggested by a model and $330\text{ }\Omega\cdot\mu\text{m}$ is a value measured from an actual device using a transmission line structure, the two numbers are not values measured with the same ruler.

How to Attach Metals

The contact problem does not end with cleaning the surface well. If we peer at the Ti-attached MoS₂ interface using a scanning transmission electron microscope where individual atoms are visible, Ti—which tries to bind strongly with sulfur—pulls sulfur away from MoS₂, creating tiny Ti/TiₓS_y clusters. The authors write that the MoS₂ layer breaking and the metal digging in are also expected. In the authors' words, this is a fundamental limit coming from the bonding and interaction at the metal-MoS₂ interface, which cannot be solved by improving deposition—the process of turning metal into vapor and thinly coating a surface.

The prescription the authors offer is metal selection. To design a truly high-mobility contact, metals or alloys must be chosen based on their bonding tendency with the MoS₂ surface, and that judgment can be advanced by increasing the number of atoms in the metal bulk while weighing the binding energy (arXiv:1807.01377, measurement + first-principles calculation).

Instead of choosing the metal, there is also the path of changing the attachment direction. Covering metal on top of an atom-thick layer is a top contact, and attaching it to the side of the layer is an edge contact. To shrink transistors properly, the length where the electrode meets the channel (contact length) must also be reduced, which is a problem that all semiconductor devices from silicon to 2D materials have yet to solve. A 2018 study made clean edge contacts on MoS₂ in situ with a direction-aligned ion beam, and the performance was maintained regardless of the contact length even when the contact length was reduced down to the 20 nm level. Among metals, chromium (Cr) turned out best, which the authors attribute to the short bond length between Cr and MoS₂.

The numbers are two, and the comparison targets are different. Compared with the top contact reduced to a contact length of 20 nm, the effective contact length was about 1 nm and the charge injection efficiency was 18 times higher. Compared with the best edge contact reported until then, the performance was about 8 times. The authors view this as experimental evidence solving the contact shrinkage problem with a clean edge interface, and write that a new path for designing devices with 2D materials opens up (arXiv:1807.08296, measurement + cross-sectional electron microscope).

Calculations sometimes point in the opposite direction. There is a calculation that solved how much the Schottky barrier is lowered depending on the angle formed between the metal and the 2D semiconductor using an electric field equation (Poisson's equation). When the contact angle increases, the section where electricity-carrying grains have escaped (depletion region) widens, which is disadvantageous, but the barrier is lowered more greatly to offset this. As a result, the contact resistance of the top contact came out lower than that of the edge contact. The same study also points out tuning factors that can reduce the Schottky barrier and contact resistance of 2D materials contacted at the edge (arXiv:2301.05373, calculation).

Measurements and calculations diverge like this. The previous experiment measured a clean edge interface made in situ with an ion beam, and this calculation solved the barrier lowering created by the contact geometry. These are not values measured with the same ruler.

Whether to attach from above or from the side may not be a settled single answer. Starting from the fundamental laws of atoms and electrons, there is a calculation that ran transmission line simulations by attaching Sc, Ag, Au, and Pd electrodes to monolayer MoS₂ in both top and edge methods using first-principles calculations. When the channel was shorter than 10 nm, direct tunneling piercing through the barrier determined the resistance, and when it was longer, thermionic emission—where electrons have enough energy to go over the barrier—determined it. Tunneling went through electronic states created inside the semiconductor's bandgap as the metal made contact (metal-induced gap states).

And the optimal strategy split depending on polarity. Holes are empty spaces left by missing electrons, and they act as grains carrying electricity. In this first-principles calculation testing four metals attached to monolayer MoS₂, top contact with a low-work-function metal turned out advantageous for n-type where electrons carry current, and edge contact with a high-work-function metal turned out advantageous for p-type where holes carry current (arXiv:2603.14296, preprint · first-principles calculation).

p-Type Transistors Are Lacking

CMOS, the standard for low-power logic circuits, pairs n-type and p-type transistors (arXiv:2409.18926). Just like the NMOS inverter we will see later, you can build a circuit with only n-types, but getting to CMOS requires p-types. However, in 2D semiconductors, it is uniquely difficult to make p-type contacts—especially low-resistance p-type contacts that let holes in well. The standard solution used in silicon is substitutional doping, where impurity atoms are densely added to the contact region; in other words, doping by replacing some of the crystal's atoms with different ones. But in p-type 2D semiconductors like monolayer $\text{WSe}_2$, the very strategy of substitutional doping in the contact region does not work (arXiv:2312.04849).

So a workaround emerged. When the same research team attached $\alpha\text{-RuCl}_3$ to monolayer $\text{WSe}_2$ to perform charge-transfer doping, the hole concentration rose up to $3\times10^{13}\text{ cm}^{-2}$ thanks to the way the two materials' energy bands are aligned (Type-III band alignment). As a result, the resistance of the junction between the p-type monolayer $\text{WSe}_2$ and the metal dropped below $4\text{ k}\Omega\cdot\mu\text{m}$ at room temperature. A p-type transistor made with this contact had a maximum current (saturation current) of $35\text{ }\mu\text{A}/\mu\text{m}$ that did not increase even when the voltage was raised further, and an on/off ratio exceeding $10^9$ (arXiv:2312.04849, measured).

A different workaround appeared for $\text{WS}_2$. $\text{WS}_2$ is expected to carry both electrons and holes well, but its valence band is relatively deep, and conventional metal contacts create electronic states right in the middle of the bandgap, making it difficult to make p-type transistors. A 2024 study used the topological semimetal NbP as a p-type electrode for bilayer $\text{WS}_2$, achieving a room-temperature hole current of up to $5.8\text{ }\mu\text{A}/\mu\text{m}$. The comparison points identified by the authors are two. It is the highest up to that point for $\text{WS}_2$ under $2\text{ nm}$ thick, and it is over 50 times larger than when using metals like nickel (Ni) or palladium (Pd).

NbP has a high work function and a low number of states where electrons can reside (density of states), which reduces Fermi level pinning. This electrode is applied via sputter deposition at room temperature, making it compatible with the CMOS process. Even so, the expression chosen by the authors is "a step toward making ultrathin $\text{WS}_2$ viable for future nanoelectronics" (arXiv:2409.18926, measured).

P-type contacts are being opened one by one through laboratory demonstrations relying on specific heterostructures or electrode materials, and judging even by these studies, there is still no universal p-type process that can be applied to just any device like substitutional doping in silicon.

A review of contact and interface engineering does not stop at counting problems, but groups the progress toward overcoming contact resistance in 2D TMD devices into four branches: interfacial interaction and hybridization, van der Waals contacts, transferring pre-fabricated metals, and charge-transfer doping (arXiv:2601.02628, preprint/review). The $\alpha\text{-RuCl}_3$ doping we just looked at belongs to the last branch.

Spreading It Evenly Across the Wafer

Making a good device out of a thumbnail-sized crystal piece and laying an even monolayer film across the entire surface of a wafer are completely different problems. Measurements from 2016 showed that monolayer MoS₂ grown by CVD exhibited transport characteristics comparable to the best exfoliated samples over a wide charge carrier concentration range (up to about 10¹³ cm⁻²) and a temperature range of 80 to 500 K. On an SiO₂ substrate at 300 K and at practical charge carrier concentrations, the monolayer mobility was about 20 cm²/V/s, and an 80 nm device recorded a current density of about 270 μA/μm at 300 K, which was the highest at the time (arXiv:1608.00987, measurement + simulation).

The authors did not stop there, and used simulations to figure out what needs to improve for monolayer MoS₂ to meet the requirements of low-power, high-performance roadmaps. And they described this result as "an important step towards large-area electronics based on monolayer semiconductors."

The reason it is uneven lies in the growth method. The core of CVD is carrying raw materials as vapor, and vapor is spatially uneven. If the metal-side raw material and sulfur-like chalcogen are not supplied in the right ratio, the location, shape, crystallinity, uniformity of the resulting crystals, and batch-to-batch reproducibility all deteriorate (arXiv:1906.05436). A 2019 study achieved three things through vapor-liquid-solid (VLS) growth, which uses a raw material with a melting point lower than the growth temperature in a liquid state: the growth of evenly sized MoS₂ pieces on a 4-inch wafer scale over an SiO₂/Si substrate, a continuous film on a 2-inch wafer scale over a sapphire substrate (with a single crystal domain size exceeding 100 μm), and site-selective patterned growth (arXiv:1906.05436, measurement).

4 inches is for scattered pieces, and a seamless continuous film is 2 inches. The two results also use different substrates (4 inches is SiO₂/Si, and the 2-inch continuous film is sapphire).

There are also attempts that go a step further from evenly laying down pieces. This is a study that chemically assembled a 2D heterostructure over a large area by connecting monolayer MoS₂ side-by-side with electrically conductive graphene. Electron microscopy revealed that the monolayer MoS₂ started growing from the edge of the graphene, forming a lateral heterostructure. Transconductance is a value representing how much the current changes when the gate voltage is changed slightly. An atomic-thickness transistor assembled this way showed a transconductance of 10 μS, an on/off ratio of 10⁶, and a mobility of 20 cm²V⁻¹s⁻¹. When circuits that invert and output the input made only of n-type transistors (NMOS inverters) were built using these devices, the voltage gain reached up to 70 (arXiv:1512.05016, measurement).

The Thinner the Electron, the Slower It Gets — Mobility and Disorder

There is an old mystery in TMDs. Compared to a bulk crystal of the same material, atomic-thickness devices have lower mobility. In a 2013 experiment measuring MoS₂ while changing the number of layers, thinning the channel down to a single layer actually caused the mobility to drop by a factor of 10. The culprit pointed to was Coulomb impurity scattering at the interface, meaning charged impurities pulling or pushing passing electrons and messing up their paths. Chemical residues, attached gas molecules, and dangling bonds on the surface are such impurities.

A dangling bond is an atomic bonding hand that has failed to find a partner and remains open. The authors wrote that the thinner the channel, the shorter the distance between impurities and charges becomes, worsening scattering, and that this factor can become the dominant scattering source beyond the vibrations of the crystal atoms (lattice vibrations) (arXiv:1308.3837, measurement + model). The thinner the channel, the more interface flaws cut into mobility.

Disorder threatens not only performance but also reproducibility and scalability. Excitons govern the properties that single-layer semiconductors exchange with light. An exciton is a state where an electron generated by absorbing light and its empty spot (a hole) attract each other and pair up, and because that electric field extends outside the single layer, it is sensitive to the surroundings. Therefore, disorder can make excitons unstable, and this instability is harmful to device performance and critical for scalability and reproducibility.

A 2026 preprint used super-resolution fluorescence fluctuation microscopy to spot unstable points within continuous single layers where fluorescence looked uniform. Those spots overlapped with the interface disorder measured by atomic force microscopy (a microscope that scans surfaces with a very thin needle to measure heights), and it was also confirmed that fluctuations decreased after heat treatment, meaning disorder was reduced. This method captures features similar to atomic force microscopy while being faster and easier to use (arXiv:2603.07418, measurement).

Defects also trap current directly. By building a graphene-MoS₂ multi-transistor structure using high-quality single-crystal single layers grown by CVD and measuring both the current-voltage characteristics of the graphene contact strips and the transconductance of the MoS₂ channel together, transport was noticeably suppressed on the n-side of the transconductance curve. The cause identified through first-principles modeling was trapping, where sulfur vacancies—empty spots missing sulfur atoms—grabbed electrons. Even though the graphene contact layer is placed between the back gate and the MoS₂ channel, the authors noted as counterintuitive that this trapping changes depending on the gate voltage (arXiv:2108.02116, measurement + first-principles model).

The Gate Insulator and a Single Gap

The final challenge is the gate insulator, which is the thin film laid between the gate and the channel. No matter how good the channel is, you cannot make a transistor if you cannot place a thin and clean insulator over it. A 2019 study clearly notes the problem. While there has been progress in finding channel materials with high mobility and a usable bandgap, finding high-quality insulators compatible with 2D technology has remained a challenge. The reasons are twofold. Commonly used oxide films (SiO₂·Al₂O₃·HfO₂) become amorphous with disordered atomic arrangements when made thin, while two-dimensional hBN suffers from too much gate leakage—meaning current leaking right through the film.

The authors extended the natural overlapping property of 2D heterostructures to fluorite (CaF₂) films grown with matched crystal orientation. A monolayer MoS₂ transistor topped with a crystalline CaF₂ insulator about 2 nm thick achieved an equivalent oxide thickness of less than 1 nm while meeting low leakage requirements, and showed a hysteresis—the degree to which the current shifts when raising and lowering the gate voltage—that was record-small at the time. The authors wrote that this is a breakthrough toward commercially competitive ultra-large-scale integration (arXiv:1901.10980, measurement).

Gate insulator materials are also called dielectrics. A review covering dielectrics notes that it is difficult to transfer dielectric integration techniques used for bulk semiconductors to atomically thin 2D materials, and diagnoses that the lack of compatible, widely scalable dielectric materials and integration techniques limits device performance and commercialization (arXiv:2402.02707, review). It has also been pointed out that the interface between the dielectric and the channel dictates virtually all performance metrics (arXiv:2509.20014, perspective).

Although several promising gate dielectrics have been reported, evaluations have been piecemeal. A perspective paper diagnoses that while there have been evaluations focusing on a few metrics like capacitive gate control, leakage, reliability, and ease of fabrication and integration with the gate stack—which bundles the gate and the film underneath it—there has been no systematic attempt to determine what makes a good gate stack. That paper aims to establish general criteria for good gate dielectrics (arXiv:2509.20014, perspective).

The contact problem and the dielectric problem largely stem from the same root. An ideal 2D crystal has all atomic bonds satisfied within its layers, leaving no open bonding hands on its broad top and bottom surfaces. Open hands remain only at the edges and defect sites. Therefore, one can envision an interface that eliminates gaps without creating new dangling bonds. In actual samples, the dangling bonds that degraded mobility were one of the Coulomb impurities remaining at the interface (arXiv:1308.3837), and dangling bonds at the edges are cited as a bottleneck when reducing channel width (arXiv:2606.04219). The fact that there are no open hands on the broad surface is a strength, but it also means it cannot form chemical bonds with the material placed on top.

A van der Waals gap is a narrow space left without chemical bonding between an atom-thick material and another material placed on top of it.

A 2025 study examined what this gap determines. This gap commonly forms at the spots where the 2D semiconductor meets the gate dielectric and the contact metal, and the gap acts as a tunneling barrier with low dielectric permittivity. Permittivity is a value indicating how well a material aligns and stretches in response to an electric field. Therefore, the effect does not go in just one direction. The same gap reduces leakage on the dielectric side, but it increases the metal-channel contact resistance and adds unwanted series capacitance (parasitic capacitance) to the gate.

The authors quantified this trade-off between suppressing leakage and the limits of reducing gate control and contact resistance. As a result, they noted that many insulators fail to meet scaling targets, and metal-channel contacts fall short of required resistances. The path they proposed is a quasi-covalent interface—a so-called "zipper-like" interface—that eliminates the gap without creating dangling bonds (arXiv:2509.17617, calculation + quantitative analysis). The "gap remaining at the interface" identified by the contact resistance model earlier as the ultimate limit is precisely this gap (arXiv:2105.10792).

An Honest Current Address

Judging by the research gathered in this article, 2D semiconductors are not an immediate replacement for silicon. Still, the evidence for their potential is clear. The background that a 2026 study stands upon is as follows. Its authors write that state-of-the-art transistors have reduced their gate length (the length of the section where the gate blankets and grips the channel) and channel thickness down to 5 nm. The abstract does not specify which device it is referring to, so this number must not be read as identical to the gate length of mass-produced chips (``What Is "3 Nanometers" the Length Of? — Measuring a Chip's Name with a Tape Measure''). However, reducing the channel width below 40 to 50 nm remained a bottleneck because dangling bonds and disorder at the edges, alongside lateral depletion, suppress the drive current (arXiv:2606.04219).

That study, a preprint, reports that it crossed this wall by reducing the width of 2D semiconductor nanoribbon transistors down to 15 nm. Contrary to the conventional scaling rule that current density worsens as width is reduced, the on-current density in single-layer MoS₂ nanoribbons improved by up to 230%, and in double-layer ones by up to 170%, stopping without rising further around the narrowest 15 nm mark. These ultra-narrow devices maintained the highest on/off ratios reported thus far at similar dimensions, and the stability of their mobility and threshold voltage also improved (arXiv:2606.04219, measured). The authors wrote that this result is promising for the ultimate miniaturization of transistors. A review on contact and interface engineering also starts from the diagnosis that traditional semiconductor technology has run into constraints in material thickness miniaturization and energy efficiency (arXiv:2601.02628, preprint and review).

However, the rivers of contact resistance, p-type doping, large-area growth, and dielectric integration have not yet been fully crossed. On one front, a path of dividing roles is visible. This is the approach of using graphene as the contact layer and TMDs as the channel. In a 2026 preprint comparing transistors in which a few layers of graphene are stacked on single-layer MoS₂ against pure MoS₂ devices with silver (Ag) contacts, charges entered more easily, and the authors wrote that viewed through band structures, charge transfer at the interface improved the alignment of energy levels (the Fermi level) and appeared to result from a reduced Schottky barrier effect. The mobility enhancement factor was about 1.6 times at 300 K and about 4.0 times at 400 K compared to pure MoS₂. The performance degradation upon raising the temperature was also clearly reduced, which the authors interpret as being because external factors such as contacts and interfaces diminished in transport across the heterostructure, bringing it closer to being dominated by lattice vibrations (arXiv:2603.19937, preprint and measured).

Graphene's place has not been closed off to a single outcome either. Up to the point cited by the study we saw earlier, graphene devices that have been demonstrated to be genuinely usable in practice were effectively micron-sized radio-frequency analog transistors and quantum Hall devices for measurement (arXiv:1202.5975, measured), and as digital switches, the cost of opening a bandgap was heavy. Still, a review of graphene transistors lists graphene both as a core candidate to replace silicon in CMOS and as a candidate for terahertz detection transistors where existing technology falls short (arXiv:2010.10382, review). The contact layer usage we just saw (arXiv:2603.19937) is added here as well.

The TMD side is similar. Demonstrations such as a single-layer microprocessor (arXiv:1612.00965) and width-reduced nanoribbon transistors (arXiv:2606.04219) are piling up, but these are pieces of evidence for potential, not mass-produced products. Reviews also organize strengths and flaws together rather than declaring a winner (arXiv:1402.0047), and a 2D materials roadmap likewise covers everything from new research domains to commercialization and standardization (arXiv:2503.22476).

The Lesson That There Were Two Walls

The story of graphene is an example of the common "hype and correction" cycle in science. One shining advantage of a material masked a single decisive weakness while raising expectations, and as data accumulated, those expectations moved to more accurate places. The correction started early. While the hype was at its peak, a review already described graphene transistors as a complement to silicon (arXiv:0911.4685). To use them as digital switches, a gap had to be opened, and in the meantime, high-frequency applications were demonstrated with terahertz and contact layer applications chosen as candidates.

Through that process, the real candidate became clear. It is TMD semiconductors, which have a bandgap even at atomic thickness. However, becoming a candidate and taking the throne are different. While microprocessors have been made almost entirely of silicon since the 1970s, the maturity of contact, doping, dielectric, and large-area processes that has been refined over that time (arXiv:1612.00965) is something 2D semiconductors have been building for over a decade (arXiv:2402.02707).

There is one lesson left by graphene. We thought there was only one wall, but there were two. The wall of having no gap was crossed by creating a gap, and behind it stood a second wall of disorder. TMD contact resistance and dielectric integration may look like that. If leakage, contact resistance, and parasitic capacitance are all caught in a single van der Waals gap, the way that gap is handled moves all three at once. However, the grounds for connecting p-type doping to that gap are not in this article. The solution is not in our hands yet, but where we need to dig has become clearer than before.

Source Papers

• "Bilayer Graphene FET" (2010) — arXiv:1001.3915 (preprint) — Room-temperature on/off roughly 100.
• "Status of Graphene Transistors" (2009) — arXiv:0911.4685 (preprint) — Complementary rather than replacement, flaws in logic.
• "Introduction to Graphene Electronic Devices" (2013) — arXiv:1309.0205 (preprint) — Inherently gapless yet requiring a gap.
• "Graphene FET Review" (2020) — arXiv:2010.10382 (preprint) — Suspended sample mobility 2×10⁵.
• "2D Materials Roadmap" (2025) — arXiv:2503.22476 (preprint) — Graphene, TMD, and MXene.
• "Structured Epitaxial Graphene" (2012) — arXiv:1202.5975 (preprint) — Yet to surpass standard semiconductors.
• "Graphene-hBN Superlattice FET" (2024) — arXiv:2405.06267 (preprint) — Moiré gap via alignment.
• "Graphene-Tellurium Heterostructure" (2023) — arXiv:2311.16792 (preprint) — Room-temperature spin-orbit gap 240 meV.
• "Bilayer Gap Signal from Metal Contacts" (2014) — arXiv:1412.1202 (preprint) — Opened gap adds resistance.
• "CVD Graphene Nanoribbon FET" (2012) — arXiv:1204.0499 (preprint) — Width 12 nm, 300 K modulation 10.
• "Epitaxial Graphene Nanoribbon FET" (2013) — arXiv:1310.6823 (preprint) — A conventional semiconductor when carefully fabricated.
• "Bilayer Graphene Tunable Gap Spectroscopy" (2022) — arXiv:2206.02057 (preprint) — 120 meV achieved by lowering disorder.
• "Semiconducting 2D TMD Device Applications" (2014) — arXiv:1402.0047 (preprint) — Strengths and flaws combined.
• "2D-TMD Contact Resistance and Interface Engineering" (2026) — arXiv:2601.02628 (preprint) — Fermi level pinning and four pathways of solutions.
• "Quantum Effects and Capacitance in Monolayer MoS₂" (2023) — arXiv:2301.03453 (preprint) — Cross-section 63~78%.
• "Two-Dimensional Semiconductor Microprocessor" (2016) — arXiv:1612.00965 (preprint) — 115 transistors.
• "Metal/2D Interface Charge Injection" (2017) — arXiv:1703.00671 (preprint) — Reported values diverge.
• "Clean MoS₂/Au Ohmic Contact" (2026) — arXiv:2605.27187 (preprint) — Interface contamination as the cause.
• "Dominant Component of Contact Resistance" (2021) — arXiv:2110.02563 (preprint) — Rjun for undoped devices.
• "Improving Electrical Contacts in 2D Semiconductors" (2021) — arXiv:2105.10792 (preprint) — 100 times the ballistic limit.
• "Contact Statistics of Synthetic Monolayer MoS₂" (2021) — arXiv:2106.08673 (preprint) — 330 Ω·μm, models diverge.
• "Atomic-Resolution Ti-MoS₂ Contacts" (2018) — arXiv:1807.01377 (preprint) — Unsolvable by deposition alone, metal selection.
• "Edge Contact Scaling Immunity" (2018) — arXiv:1807.08296 (preprint) — 18 times compared to top 20 nm.
• "Phase Charge Lowering in 2D Schottky Barriers" (2023) — arXiv:2301.05373 (preprint) — Top lower in calculation, with edge improvement factors as well.
• "First-Principles Transmission Line Tunneling Limit" (2026) — arXiv:2603.14296 (preprint) — n-type top, p-type edge.
• "p-Type Monolayer WSe₂ Ohmic Contact" (2023) — arXiv:2312.04849 (preprint) — Bypassing charge transfer doping.
• "WS₂ p-Type Conduction via NbP Contacts" (2024) — arXiv:2409.18926 (preprint) — Over 50 times compared to Ni and Pd.
• "Performance Projections for Synthetic Monolayer MoS₂" (2016) — arXiv:1608.00987 (preprint) — 270 μA/μm, one step.
• "VLS Wafer MoS₂ Growth" (2019) — arXiv:1906.05436 (preprint) — 4-inch pieces and 2-inch films.
• "Chemical Assembly of Atomically Thin Circuits" (2015) — arXiv:1512.05016 (preprint) — Lateral heterostructures, gain 70.
• "Thickness-Dependent Interfacial Coulomb Scattering" (2013) — arXiv:1308.3837 (preprint) — 10-fold drop in mobility at monolayer.
• "Imaging Monolayer Disorder Fluctuations" (2026) — arXiv:2603.07418 (preprint) — Reduction of fluctuations through annealing.
• "Graphene-MoS₂ Multi-FET" (2021) — arXiv:2108.02116 (preprint) — Sulfur vacancy trapping.
• "CaF₂ Insulating Layer" (2019) — arXiv:1901.10980 (preprint) — Amorphous oxide film, hBN leakage.
• "Dielectrics for 2D TMDs" (2024) — arXiv:2402.02707 (preprint) — Lack of dielectric integration technology.
• "Gate Dielectric Screening" (2025) — arXiv:2509.20014 (preprint) — Fragmentary evaluations.
• "Scaling Constraints of Van der Waals Gaps" (2025) — arXiv:2509.17617 (preprint) — Leakage down, resistance and capacitance up.
• "Breaking Through the 2D Nanoribbon Width Scaling Wall" (2026) — arXiv:2606.04219 (preprint) — Width scaled down to 15 nm.
• "Graphene-MoS₂ Vertical Heterostructure" (2026) — arXiv:2603.19937 (preprint) — Mobility improvement over pure.