Next-Generation Memory — The DRAM Wall and the Race for a "Dream Memory"

Over 20 Volts for More Than 3.5 Milliseconds, Exactly the Same for Every Erase

Photos and apps on phones and laptops are stored in a storage device called an SSD, and NAND flash is the chip inside the SSD that holds onto data. NAND flash is a memory that keeps its contents even when the power is turned off, and an entire block must be erased at once before new data can be written. When an SSD erases a block of NAND flash, it applies a voltage exceeding, for example, 20 volts to a cell—the smallest compartment that holds data—for a duration exceeding 3.5 milliseconds. During this time, the cells wear out slightly, and user read and write requests can be delayed.

Deciding what this erase time should be was the starting point of a 2024 study. According to the authors, no study until then had delved into what that time should have been set to in the first place. Almost all existing techniques used a single fixed time for every erase, and that value was determined to cover even the worst-case operating conditions.

The authors made the erase time adjust to the current state of the cell. At the start of the erase, they briefly apply a short pulse of about 1 millisecond, count the bits that are not yet erased, and predict the appropriate time. A bit is a single digit of 0 or 1. Building on this, they aggressively, yet safely, harness the large reliability margin remaining in modern SSDs. Across 160 actual 3D NAND chips with vertically stacked cells, the SSD lifespan increased by 43% compared to the conventional method, without modifying a single NAND chip. In a system-level evaluation run with 11 real workloads, the waiting time for reads that finish the slowest—that is, the read tail latency—was also reduced by an average of 34% compared to the latest technique (arXiv:2404.10355, actual chip measurements + system-level evaluation).

This means that much margin was left over. That margin lay within a single fixed time that tailored every erase to the worst-case operating condition, along with the large reliability margin remaining in modern SSDs.

Memory—the chips that hold data to be used for computation and hand it over when needed—is placed in layers inside a computer. SRAM at the top is the fastest memory placed inside the processor, creating a cache: a small, fast storage space that brings data close to the processor to be used again soon. Below that is DRAM, the main memory, which holds data while the computer works and loses its contents when the power is turned off ("Fetching Is Slower Than Computing — The Memory Bottleneck and HBM"). At the very bottom is NAND flash. The higher you go, the faster it is, but the more expensive and smaller it becomes.

There is one more property that divides these three layers. Non-volatility is the property where stored values remain intact even when the power is cut off. NAND flash is non-volatile, while DRAM and SRAM are volatile memories that lose their values when the power is cut off.

Each of these three layers carries its own trouble. One comparison tool that weighs memories put inside a chip writes down those troubles in two directions: in data-intensive applications, repeatedly accessing off-chip DRAM drives up operating power, while in SRAM, process miniaturization and leakage power limit efficiency (arXiv:2109.01188). Leakage power is the power consumed by leakage current—the current that leaks out even when a transistor is in the "off" state—and this current grew larger as switches became smaller ("A Transistor Is a Switch — A Tiny Faucet You Open and Close with Electricity").

Thus, an old dream was summoned back: a "universal memory" that solves everything with a single memory. This article first looks at why DRAM is becoming harder to shrink and what NAND encountered as it stacked upward. Next, it looks at what four candidates—MRAM, PCRAM, ReRAM, and FeRAM—can and cannot change, arriving at a slightly different question. Before asking what won, what we must ask first is what we should measure it with.

All papers cited here are arXiv preprints, mixing those that have passed through conferences and journals with preprints before peer review. Measured values from experiments and calculated values are also mixed, so for each heavily weighted spot, which one it is is noted in parentheses.

DRAM — Knock on Your Neighbor and the Next Row Flips

The fundamental weakness of DRAM is that it forgets. A DRAM cell holds a value in a capacitor, a tiny bowl that stores electrical charge, and that charge slowly leaks away. Refresh is the operation where DRAM periodically reads and refills the stored contents so it does not lose values.

Refresh is a problem that miniaturization makes heavier. A 2023 retrospective reviewing a 2012 paper defines refresh as a problem of technology miniaturization. This is because as DRAM cell sizes shrink and chip capacities grow, the side effects of refresh—using energy and degrading performance—worsen. This means that making things smaller does not solve the problem by itself, and as things get smaller, the problem gets heavier.

The solution reviewed in the same retrospective looks just like the introduction's eraser story. DRAM cells are arranged in rows like a checkerboard, and the minimum time required to hold onto data differs for each row. Therefore, rows are grouped according to their minimum retention time, which row belongs to which group is stored in a cheap data structure called a Bloom filter, and each group is refreshed at a different cycle. Evaluations in the original paper and follow-up studies showed that performance and energy efficiency improved significantly, and those gains grow larger as chip capacity increases (arXiv:2306.16024, retrospective paper).

Miniaturization produced other self-inflicted wounds, too. When reading and writing, DRAM opens an entire row at once. This act of opening a row is called activation. RowHammer is a phenomenon where repeatedly opening and closing a single row of DRAM physically flips bits in nearby neighboring rows. A variant reported in 2023 required far fewer knocks. RowPress is a phenomenon where merely leaving a row open for a long time disturbs neighboring rows and flips bits.

RowPress reduces the number of activations needed to flip bits by one to two orders of magnitude—that is, from ten to one hundred times—under realistic conditions. In extreme cases, a bit flipped with just a single activation of an adjacent row. Characterizing 164 real chips of DDR4, a type of DRAM specification, yielded three findings. First, the phenomenon appeared in chips from all three major DRAM manufacturers. Second, it grew more severe as DRAM technology descended to smaller nodes. A node is a name attached to a generation of semiconductor manufacturing process (What Is "3 Nanometers" the Length Of? — Measuring a Chip's Name with a Tape Measure). Third, RowPress affects different cells than RowHammer and responds differently than RowHammer when temperature and access patterns change (arXiv:2306.17061, real-chip characterization).

The authors demonstrated two things on a real DDR4 system with RowHammer defense turned on. First, an ordinary program with only user privileges could flip bits using RowPress, whereas conventional RowHammer could not accomplish the same thing. This means RowPress succeeded even when RowHammer defense was turned on in that system. Second, when the memory controller—the circuit on the processor side that issues commands to DRAM—kept rows open longer depending on access patterns, it actually aided the RowPress attack. Keeping rows open longer is an optimization introduced for performance. The authors also proposed a methodology to adapt existing RowHammer countermeasures to block RowPress as well with a low performance overhead (arXiv:2306.17061).

Some analyses suggest that the walls do not lie solely within the technology. One analysis views that while half a century of improvements seated DRAM in the primary memory spot, moving past today's miniaturization problems requires makers and users to move together. The authors diagnose that the separation of roles between producers and consumers established by industry-wide DRAM standards is becoming a stumbling block to progress. The directions they examined are four: latency improvement, reduction of refresh overhead, RowHammer defense, and worsening memory errors. The authors note that in all four cases, the single biggest barrier was that users cannot look into the reliability characteristics of DRAM. Therefore, what they proposed is also limited information transparency between producers and consumers, and the plan has two stages. First, release information directly through crowdsourcing and paper publications, and ultimately, widely revise the DRAM standard (arXiv:2401.16279, analysis and proposal).

The burdens of miniaturization shown by the studies in this section are two: as cells become smaller and chip capacities grow, the side effects of refresh worsen, and RowPress measured on real DDR4 chips grew more severe as moving to smaller nodes.

NAND — When We Stacked It Up, Every Layer Was Different

NAND flash took a different path. Instead of drawing things smaller on a flat plane, 3D NAND stacked dozens of silicon layers vertically. Thanks to this, it could pack more onto the same chip even with a much less aggressive process. However, as the cell designs, circuits, and structures changed, the ways in which various error sources affected reliability also shifted dramatically.

When actual 3D NAND chips were characterized, three error sources emerged that did not exist in planar NAND. The first is layer-to-layer process variation. Layer-to-layer process variation is a phenomenon where the average error rate clearly differs across the vertically stacked layers within a single chip. The second is early data loss, where errors caused by electric charge leaking within a few hours after writing (programming) data increase rapidly. The third is retention interference, where the speed at which charge leaks from one cell varies depending on the values stored in neighboring cells.

The authors organized these observations into analytical models for layer-to-layer variation and retention loss, and built four countermeasures that can complement and be used together. Using all four together extends flash lifespan by 1.85 times compared to the latest baseline. If you choose to keep the lifespan as it is, the storage overhead for error-correction information—that is, the information added and written to immediately fix bits read incorrectly—is reduced by 78.9% instead. You do not get both gains at the same time, but choose which direction to use them (arXiv:1807.05140, real-chip analysis + technique proposal).

Squeezing density further leaves less margin. QLC NAND, which packs 4 bits into a single cell, broadens storage density at the cost of narrowing the read margin—the leeway to distinguish values within a single cell from one another. Within that narrow margin, what torments QLC is lateral charge migration. This is a phenomenon where charge densities are uneven between neighboring cells, causing charge to move sideways. Existing countermeasures like WBVM and DVDS changed the layout inside pages, which are bundles of data that NAND reads and writes at once. One research team observed that the arrangement between pages also produces the same effect, and had an LSTM neural network guided by physical knowledge determine the arrangement. The bit error rate dropped by an average of 80.4% compared to no arrangement at all, and by 18.4% and 15.2% at a code length of 64 compared to the existing techniques WBVM and DVDS, respectively. Unlike the two existing techniques, it does not even require flag bits to record how the data was moved (arXiv:2511.00075, technique proposal and experimental evaluation).

If you line up the walls that have appeared so far, their shapes overlap. On one side, there are things where neighbors interfere with neighbors. Rowhammer, rowpress, retention interference in 3D NAND, and lateral charge migration in QLC all have different mechanisms, but the results are the same. On the other side is the fact that cells within the same chip are different from one another. There are minimum retention times that differ by row, error rates that differ by layer, and erase characteristics that differ by cell state. The margins we saw earlier mostly arose from places where those differences were ignored and unified into a single value.

Why the "Dream Memory" Has Been a Long-Standing Goal

Then what if we stopped dividing layers? Universal memory is a single memory that is as fast as SRAM, keeps data even when the power is turned off like NAND, is as dense as DRAM, and does not wear out no matter how many times it is rewritten. The "dream memory" in the title is this, and it is the long-sought goal of non-volatile memory research.

The candidates fail to check all of these boxes at once, and the way they fail is regular. As summarized in a review mapping out non-volatile main memory technologies, these technologies generally gain high density, byte-level access, non-volatility, low cost, and energy efficiency at the cost of long write latencies, high write power, and limited write endurance. Byte-level access means you can pick and choose just the few bytes you need to read and write. The gains are clustered in density, non-volatility, and cost, while the losses are clustered in writing. The authors viewed that by 2020, these technologies had already become competitive alternatives to DRAM and would fundamentally change the landscape of memory systems (arXiv:2010.04406, review).

The same review divides the research into memory architecture, data persistence, performance improvement, energy reduction, and wear leveling. Wear leveling is a design that evenly distributes writes across cells so that a single spot does not wear out first. The challenges pointed out by the review lie outside the devices themselves: system architecture design, operating system memory management, and programming models for hybrid systems that mix multiple types of memory. What the authors introduce as their own work is also the design of hybrid memory systems.

This field also has the circumstance that physical devices are hard to come by. A tutorial covering novel memory modeling starts by positioning non-volatile memory as a promising alternative to conventional volatile memories like SRAM and DRAM, noting that because physical devices are rare, simulators play a decisive role in architectural exploration and hardware-software co-design. The hybrid main memory and caches, in-memory computing, and wear-leveling designs that this tutorial covers as four case studies demonstrate the core interests of this field (arXiv:2502.10167, tutorial and tool release).

The comparative tool that noted the difficulties of DRAM and SRAM in the introduction is that very tool, and its target is limited to non-volatile memory embedded in chips. The premise of this tool is that each candidate technology produces different trade-offs in density, reading, writing, and reliability. Therefore, the authors built a framework to quantify those trade-offs alongside realistic system constraints and application-level impacts, evaluating them in settings such as edge-device machine learning, graph analytics, and general-purpose cache hierarchies. The users envisioned by this framework are application experts, system designers, and device experts all three (arXiv:2109.01188, framework). The fact that a separate tool was built for all three groups to use together can be read as meaning that the calibration of this field had not converged into one by that point in 2021.

The dream is one, but the paths are at least four. Let us ask the same two questions to the four candidates. What holds the 0s and 1s, and what do you trade away in return?

MRAM — The Property of Flipping Probabilistically Is Both a Defect and a Resource

MRAM (Magnetoresistive Random-Access Memory) is a memory that stores information in the magnetization direction of magnetic layers created by the spin of electrons instead of electric charge—in other words, the direction pointed to by a tiny magnet. The magnetic tunnel junction, which is its core component, consists of two magnetic layers with a very thin insulating film sandwiched between them, and its electrical resistance varies depending on whether the magnetization directions of the two layers are the same or opposite. Therefore, MRAM holds 0s and 1s in its magnetization directions, and because the direction of the magnet stays the same even when the power is turned off, it is non-volatile.

The grounds for naming MRAM as a candidate for universal memory include near-infinite endurance, low read and write latency, ultra-low-power operation, high density, and CMOS process compatibility. The CMOS process is the standard silicon process used to make chips today. This list was written as background in the first sentence of a paper, and what that paper actually did was far removed from making memory.

What the authors aimed at was the defect side of MRAM. A magnetic tunnel junction inherently flips probabilistically, and the authors attribute the cause to a combination of factors intrinsic to the device and process variations. Even when the same current is passed for the same time, some cells flip and others do not. The authors manipulated the write latency of a commercially available MRAM chip to extract that probabilistic nature, and with it extracted true random numbers—that is, truly unpredictable random numbers. To the authors' knowledge, this is the first system-level implementation using a commercial toggle MRAM, and the authors report that running NIST randomness tests shows this method is robust under a wide range of operating conditions and fast enough at roughly 22 megabits per second even in the worst case (arXiv:2104.00198, commercial chip measurement).

The same probabilistic nature is described as a wall to be overcome in another paper. STT-MRAM is a method that flips magnetization using the spin of a current flowing straight through a cell. This method is attractive for its non-volatility, fast operation, and high endurance, but it also has limitations. Switching is probabilistic, and the critical switching current—the minimum current required to flip the magnetization—is high. When the current is high, it is difficult to use for ultra-high-speed operation on the scale of nanoseconds and shorter.

The SOT method that emerged as a result flips magnetization using the torque created by an in-plane current flowing sideways in the layer beneath the magnetic tunnel junction. There is a price attached to this. The SOT-MRAM cells studied up to that point use three terminals to apply the in-plane current, and as a result, the cells become large. Every method tried to overcome the wall of current and speed ends up sacrificing cell area instead. What this paper created is a cell with two terminals. When a CoFeB/MgO magnetic tunnel junction pillar is erected on top of a very thin and narrow tantalum underlayer, applying a single voltage generates both an in-plane current and an out-of-plane current simultaneously. The authors show that switching is primarily caused by SOT, and then report that the critical write current is reduced by over 70% compared to an STT-MRAM cell made with the same structure (arXiv:1806.09713, device measurement).

There are also attempts looking further ahead. This is a magnetoresistive memory in which all layers are made of two-dimensional materials just a few atoms thick ("2D Semiconductors — Graphene's Betrayal and the Real Candidate for the "Post-Silicon" Era"). Reading is done via tunneling magnetoresistance like the earlier magnetic tunnel junction, but the writing was changed. When a current is sent through one layer, the orbital magnetic moment of the electrons tilts to one side and imparts torque on the magnetic layer. While STT and SOT rely on spin momentum, this orbital-transfer torque uses orbital momentum perpendicular to the plane. Thanks to this, it was able to flip perpendicular magnetization at room temperature using only interfacial current without an external magnetic field, and the authors view this approach as promising for low-power, high-performance memory (arXiv:2312.01269, device demonstration).

There are also designs that bypass weaknesses rather than fixing them. This is a proposal that mixes STT-MRAM into the L1 data cache of a GPU—a processor responsible for graphics and massively parallel computing. By predicting which data will be read and how often using information obtained during execution, blocks that are written once and read multiple times are put into STT-MRAM, while blocks that are rewritten multiple times are left in a small SRAM. The write weakness is left as is, and only data with low writes is selectively packed. In evaluations, memory references crossing the interconnect network inside the GPU decreased by 32%, performance increased by 217%, and energy decreased by 53% compared to conventional GPU caches (arXiv:1903.01776, architectural proposal and simulation evaluation).

MRAM holds 0s and 1s in its magnetization direction, and in the STT method, the price for that is the write. Flipping takes a large current, and the flipping is probabilistic. SOT and orbital-transfer torque are alternative writing methods aimed at reducing that current, and the probabilistic nature was used as a wall in one paper and as raw material for random numbers in another.

PCRAM — What Remains in a Mature Technology

PCRAM (phase-change RAM) is a memory that stores information by switching a material between a crystalline state and an amorphous state. The crystalline state is one where atoms are neatly lined up, while the amorphous state is one where atoms are tangled together. The electrical resistance of the two states is very different, and that difference becomes 0 and 1. The phase is changed by heating the cell with an electric current.

A 2010 comprehensive review assesses that this technology matured rapidly in a short period. It notes that it outperformed previous-generation technologies both in precise demonstrations scaled down to small dimensions and in large-scale array demonstrations equipped with retention, endurance, performance, and yield. Yield is the ratio of usable products among those made, and an array is an arrangement where cells are laid out in large numbers like a checkerboard. The strengths the review highlights are scalability and fast switching.

The list of challenges that the same review writes down next is long. On the manufacturing side, it points out reset current—the current required to turn the cell amorphous—cell designs to lower it, and the control of variability where characteristics scatter from device to device. There is also one unexpected item: the manufacturing process itself can cause undesirable changes in the phase-change material. In the operation phase, data retention, endurance, bias polarity effects, and thermal crosstalk between devices follow. Because it is a technology that heats the cell to change its phase, that heat spreads to neighboring cells. "Neighbors disturb neighbors" from the previous section appears here as well. The review lists methods to pack multiple values into a single cell through intermediate resistance states, encoding, and the path toward ultra-high density as future enhancement factors (arXiv:1001.1164, comprehensive review as of 2010).

PCRAM also directly targets the territory of DRAM. This is because it is non-volatile, has zero leakage power, and has higher cell density, longer retention time, and easier capacity scaling than DRAM. However, conventional PCM (another name for PCRAM) controlled by electricity has a longer write latency and higher write energy than DRAM, and the values that can be packed into a single cell are capped at 2 bits. That is the trade-off summarized by the review in the previous section.

Thus, a path emerged to touch the cells with light instead of electricity. PCM cells with optical control, demonstrated earlier by other researchers, support 5 bits per cell and access the cells directly using light signals carried on silicon optical wiring. However, this paper notes that there is a price to pay. Because it accesses the cells directly with light signals, such a system cannot be designed with conventional memory architectures, and the architecture must be redesigned from scratch. The architecture the authors built on top of that cell, COSMOS, places new read and write protocols on a hierarchical multi-bank array, and exchanges signals with the processor via electro-optic-electric conversion units. As a result of evaluating a 2.5-dimensional integrated system containing both the processor and COSMOS, it was an average of 2.14 times faster than electrically controlled PCM, with 3.8 times less read energy per bit and 5.97 times less write energy per bit (arXiv:2107.11516, architectural proposal and simulation evaluation).

On the miniaturization side, results simplifying the materials have emerged. A common strategy to refine the properties of phase-change materials is to mix multiple additive elements in precise ratios, which frequently results in four-element compounds or even more complex substances. However, a single element such as antimony also became a viable alternative when confined to an extremely small volume. When the composition is simple, the problem that worsens as devices are aggressively scaled down—namely, the composition deviating from the optimal ratio in the tiny volume where switching occurs—disappears. The authors take just one step further here, writing that it might make it possible to harness nanoscale effects for information storage (arXiv:1902.00254, device demonstration).

Time is also a weakness. The electrical resistance of a stored cell changes gradually over time, as if drifting. This non-ideality harms the precision achievable when computing inside memory with phase-change devices. A promising countermeasure raised by the authors is an architecture that projects the phase arrangement onto stable elements within the device, and they investigated this projection mechanism in a representative phase-change memory structure called the mushroom type. They measured the state-dependent resistance, the drift coefficient (the degree to which resistance drifts over time), and the phase arrangement using nanoscale projected Ge2Sb2Te5 devices, revealing how these devices fundamentally operate (arXiv:2105.13693, physical device measurement).

PCRAM stores 0s and 1s in the state of atomic arrangements, and in exchange, it bears longer write times, higher write energy, and heat spreading to neighbors compared to DRAM. Resistance that drifts over time harms precision when computing inside memory.

ReRAM — Is Resistive Random-Access Memory a Memristor?

ReRAM (resistive random-access memory) is a memory that changes resistance by applying a voltage to an insulating material to create or break conductive pathways (filaments) inside. Because resistance is low when the pathways are connected and high when they are broken, 0s and 1s are stored in whether pathways exist or not. This article covers this filamentary type, though there is also a method where resistance changes at the interface without pathways. Its simple structure makes it advantageous for integration.

A 2017 study set down in its first paragraph what the commercialization of this technology depends on. Transition metal oxide ReRAM is being intensively developed as a memory targeting storage-class memory—in other words, the space between DRAM and storage—due to its good operating power, endurance, speed, and density, but its commercial deployment depends crucially on a predictable model that understands nanoscale physicochemical forces. That understanding had been vague and controversial up to that point. This is because it is difficult to directly see how atoms move during switching.

So this team looked inside hafnium oxide devices while they were operating using synchrotron X-ray absorption spectroscopy. What appeared were local conductive pathways caused by oxygen deficiency, and a low-conductivity ring of excess oxygen surrounding those pathways. It appears that oxygen was pushed out of the pathways and accumulated at the edges. When heat treatment was subsequently applied, the separated oxygen mixed evenly again, returning the cell to the resistance state from when it was first manufactured. The authors showed that the process of pathways forming and disappearing is well modeled by two movements driven by the heat generated by the current: radial thermophoresis and Fickian diffusion. Thermophoresis is a phenomenon where atoms move along a temperature gradient, and Fickian diffusion is diffusion where substances spread from areas of high concentration to low concentration. They are two nanoscale forces competing in opposite directions (arXiv:1701.00864, measurement + modeling).

There are also results in extreme environments. An Al2O3/TiO2-x crossbar device succeeded in resistance switching from room temperature, 300 kelvins, down to 1.5 kelvins. Between 130 kelvins and 1.5 kelvins, a negative differential resistance—where current decreases even as voltage is increased—appeared in the current-voltage curve, and the authors attribute this to a metal-insulator transition of the Ti4O7 conductive filament. The curve became highly nonlinear, raising the ratio of the on-current to the off-current up to 84 at 1.5 kelvins. The authors concluded that this paves the way to build cryogenic passive crossbars—arrays with only cells at each point where horizontal and vertical electrodes intersect—without selection devices attached to every cell, and added that conduction in the low-resistance state suggests a hopping-type mechanism (arXiv:1908.05545, device measurement).

There is also an experiment in this field that put the name itself to the test. It is often said that "all resistive random-access memories are memristors." According to its original formulation, a memristor is a hypothetical, ideal device whose resistance depends solely on the net charge that has passed through the device. Regardless of how fast or when the charge passed, it means that only the net charge—obtained by subtracting the amount returned from the amount that passed in one direction—determines the resistance.

In 2019, a clear test to judge whether a physical system is truly a memristor was proposed by other researchers. One team applied that test to both a Cu-SiO2 cell they built and a commercially available electrochemical metallization cell. The result was clear. They were not memristors. The authors themselves reveal how far their conclusions can be extended. Because these cells share characteristics similar to many other memory cells, the claim that "all resistive random-access memories are memristors" is refuted. Furthermore, they cast doubt on whether an ideal memristor can exist as a physically producible device, and formalize two conjectures that it is impossible to describe actual resistive random-access memories with memristor models (arXiv:1909.07238, device measurement).

The question of whether what a name points to and the actual object are the same is also a question that "After Moore's Law — What a "Nanometer" Came to Mean" raised regarding process names. ReRAM stores 0s and 1s in whether pathways exist or not. Up to the point of the preceding study, the predictive models needed for commercialization were without a full understanding of the principles by which pathways form and disappear, and the two forces confirmed by that study were presented as building blocks for future models.

FeRAM — The Same Defect Is the Culprit and the Resource

FeRAM (ferroelectric memory) is a memory that stores information in the polarization direction of a ferroelectric material. Polarization is a state where positive and negative charges inside a material are biased and lined up to one side, and a ferroelectric material is a substance that maintains this bias on its own and can flip its direction with electricity. A direction once pushed by electricity remains even when the power is cut off, and 0s and 1s are contained in which way the polarization points.

What changed the game was the discovery that hafnium dioxide (HfO2) exhibits ferroelectricity. Hafnium dioxide fits well with silicon processes, and its polarization unexpectedly and stubbornly remains even in very thin films. Yet why this happens was still under debate as of 2021. The polar phase that produces ferroelectricity is a metastable state—meaning it is holding on, but not the most stable state—and the most stable ground state in bulk form is the non-polar one. If left to its natural tendency, ferroelectricity should disappear, yet it was found to persist in thin films and later even in bulk form. The explanations until then were that it was the result of overlapping external factors like stress, grain boundaries, and oxygen vacancies, along with phase transition dynamics during heat treatment. An oxygen vacancy is a site left empty when an oxygen atom escapes.

A first-principles calculation study—which calculates material properties starting from the laws of quantum mechanics without experimental values—points to a different culprit: doubly charged oxygen vacancies, a defect common in binary oxides yet overlooked, are decisive in stabilizing the polar phase. The emphasis is less on the mere presence of defects than on the charge state of those defects, and the authors write that this charge state becomes a new degree of freedom that tunes the thermodynamic stability of competing phases in wide-bandgap oxides (arXiv:2106.12159, first-principles calculation).

Putting ferroelectrics into a transistor turns a single device into memory. A transistor is a switch that opens and closes the path of current using a voltage applied to the gate—a piece mounted on top of the channel with a thin film in between. An FeFET is a device where a ferroelectric is sandwiched in place of the insulating film under the gate, making its polarization direction remember the on/off state of the transistor. As of 2021, the application where this device was being actively reviewed as a strong candidate was 3D NAND memory.

Looking at the numbers alone, the potential is clear. Ferroelectric HfO2 shows data retention of over 10 years, endurance exceeding 10¹² cycles, polarization switching under 1 nanosecond, and remnant polarization of 10 to 30 μC/cm². However, these figures are for a capacitor with a ferroelectric film sandwiched between two electrodes. The performance of an actual FeFET was known to be much worse than a ferroelectric HfO2 capacitor, and the reason was not fully understood.

A modeling study starts from that discrepancy. The authors built an FeFET model on the framework of charge neutrality, examining how charge neutrality and leakage-assisted switching mechanisms operate in a gate structure where metal, ferroelectric, dielectric, and semiconductor are stacked. The conclusion shifts the location of the bottleneck. What determines memory characteristics is not the ferroelectric layer, but the interface between the ferroelectric and the dielectric, and the dielectric layer itself. The authors write that experimental FeFETs are well explained by this model, and the mismatch between capacitors and FeFETs has been successfully understood (arXiv:2105.12892, modeling).

An even more aggressive device has also emerged. A study integrating HfO2/ZrO2 ferroelectric nanolayers simultaneously onto a CMOS interconnect process (BEOL) and SiO2/Si achieved nanosecond multi-level writing at under 5 volts. The interconnect process is the stage where metal wiring layers are built on top after the transistors are fully made, and multi-level writing is writing that divides and stores more than two values in a single cell.

Using partial polarization switching—which does not flip the polarization all the way—pushed endurance above 10¹¹ cycles, creating a capacitance state featuring non-destructive reading (where the value is not erased when read) and 10-year retention. However, the experiments also exposed a wall. When the read frequency exceeded 1 MHz (meaning one million times per second), the capacitance window collapsed. The authors bypassed this speed limit by using a 20-picosecond pulse—shorter than the device's RC time constant, which is the time it takes for a device to follow voltage changes—to measure the leakage current that varies according to polarization. The energy spent per read was 14 femtojoules (arXiv:2606.03677, device measurement).

The device that most directly meets the dream of a universal memory also comes from here. Non-volatile SRAM is an attempt to compensate for each other's two weaknesses: the high standby power of CMOS SRAM and the long write latency of emerging non-volatile memories. Yet conventional designs typically required a backup-and-restore operation that copies the contents of the SRAM to the non-volatile side and brings them back, imposing a heavy cell area penalty. One proposal solves this with a 4-transistor structure combining two cross-coupled FeFETs and two access transistors. It is smaller than conventional 6-transistor SRAM. By simply changing the write conditions, the same cell operates in either volatile mode or non-volatile mode. In non-volatile mode, it used a 2-nanosecond storage time and 0.13 microwatts of retention power, requiring no separate backup-and-restore operation (arXiv:2606.19918, device and circuit proposal).

The exact same material is used in the exact opposite way. As non-volatile memory research gained momentum, the phenomenon where polarization spontaneously relaxes drew attention instead. One study suggests that understanding the physics governing retention time opens an opportunity to optimize devices either for non-volatile memory or for real-time signal processing where a predetermined time constant is critically important. A time constant is the time representing how long a value holds out before disappearing. The authors write that such a device could be an elegant solution to realize nearly arbitrary time constants within a single scaled memory device, opening the path to time-handling computing and brain-inspired computing.

What they built as a result is a ferroelectric capacitor stack with intentionally defected interfaces. Thanks to an internal electric field holding one polarization direction in place, the unstable polarization state lasts on the millisecond scale before vanishing. Because the retention time depends on both the polarization state and electrical stimuli, multiple time scales could be used in a single device, and the authors cite the role of oxygen vacancies as a possibility for the source of this internal electric field (arXiv:2508.08973, device measurement).

Oxygen vacancies, which earlier were pointed to as the side that locks in ferroelectricity, appear here as candidate sources for the side that leaks data and controls time. What started as a pursuit of non-volatility deliberately produced volatility, and what made that difference was the state of the interface.

FeRAM contains 0 and 1 in the direction of polarization. The prices faced by the studies in this section are twofold: performance measured in capacitors did not translate directly to FeFETs (a model explained why), and a capacitance device saw its window collapse during fast reads (which the same study bypassed with shorter pulse reads).

When Memory Met Computation

The ambition of next-generation memory does not stop at taking over the seats of DRAM and NAND. The state where computing devices keep getting faster, but the speed of fetching data from memory fails to keep up, so waiting rather than computing determines performance—namely, the memory wall ("Fetching Is Slower Than Computing — The Memory Bottleneck and HBM")—strives from a computer architecture where the computing part and the data-storing part are separated. We call this structure the von Neumann architecture. Thus, the idea emerges: rather than fetching and carrying data, let us finish the computation right in the place where the data is stored. "Don't Move It, Compute Where It Sits — Six Questions Left After We Made Memory Do the Math" follows this very idea.

As Moore's Law—the observation that the number of transistors packed into a single chip doubles every fixed period—fades, forecasts have emerged that the improvements in computing performance gained from miniaturization will not be large. One review therefore raises the question of whether the progress of artificial intelligence might slow down or stall because of hardware limitations, and reviews as a candidate for the answer ReRAM-class devices, which this review calls memristors (arXiv:2004.14942, review). The spots targeted by the authors are three: energy-efficient in-memory computation, deep learning accelerators, and spiking neural networks that compute by exchanging short electrical signals like the brain's neurons. However, what the authors pick as the central theme does not stop at the device. It is that we must lean on a non-von Neumann architecture, and that we must separately develop learning and inference algorithms suited for it.

One research team implemented a hyperdimensional computing system that finishes computation inside memory atop 760,000 phase-change memory devices. Hyperdimensional computing is a calculation method that handles very large patterns within memory and compares them with each other to learn and classify. This system achieved accuracy comparable to software across three tasks: language classification, news classification, and hand gesture recognition from electromyogram signals. The reason this calculation method was chosen is that the core property of this approach is robust to imperfections in the physical substrate in charge of computation (arXiv:1906.01548, device demonstration). It chose a calculation method that endures imperfections rather than fixing them, sharing the same shape as the "bypassing weaknesses" design seen in the MRAM section.

Light and Atomic Thickness — The Stage Gets Wider

There is another field blocked by the lack of memory. Photonic integrated circuits are chips that handle signals with light, boasting a large bandwidth—that is, the amount of data that can be moved per unit time—low latency, and inherent parallelism. Yet one review notes that the absence of an efficient, scalable non-volatile memory device remains a fundamental limitation for fully programmable optical systems. Attaching electronic memory causes conversions between light and electricity to repeat, bringing energy consumption and latency along with them.

That is why non-volatile optoelectronic resistive memory, which combines resistive switching with optical reading, has emerged as a candidate. The list of switching mechanisms organized by this review is filamentary conduction, interfacial switching, phase-change transition, and ion migration. Several principles that followed from the preceding ReRAM and PCRAM sections appear again. The difference is that interaction with confined light is layered on top, and therefore an item is also added to the axes of comparison. To switching energy, speed, and endurance is added optical modulation efficiency, which means how well it changes light (arXiv:2606.01463, review).

Results have also emerged from the atomic-thickness material side. A non-volatile memory built by stacking MoS2/h-BN/multilayer graphene features an atomically flat interface and a write/erase speed of approximately 20 nanoseconds. The highest-level flash memory cited by the authors for comparison sits at roughly 100 nanoseconds (arXiv:2009.01581, device demonstration). This abstract contains no retention time or endurance figures.

So What Should We Measure With?

None of the studies cited here report a candidate that has completely replaced DRAM and NAND. The same review views these technologies as competitive alternatives to DRAM, citing the design of systems mixing multiple types of memory as a challenge (arXiv:2010.04406). The settings where the cited studies test their candidates are each suited to their strengths. They are embedded memory in chips, cache, storage-class memory, and accelerators that mimic brain-like computing and compute right in memory.

The challenges noted by the cited studies at their respective points in time are as follows. For MRAM, the critical write current and probabilistic switching of the STT method were pointed out (arXiv:1806.09713, arXiv:2104.00198); for PCRAM, the reset current, write energy, and resistance drift over time were noted (arXiv:1001.1164, arXiv:2107.11516, arXiv:2105.13693). ReRAM lacked the understanding needed as a foundation for predictive models, and debates surrounding its name remained (arXiv:1701.00864, arXiv:1909.07238). For FeRAM, the origin of ferroelectricity was under debate, and the gap between the capacitor and the device was explained by a single model (arXiv:2106.12159, arXiv:2105.12892).

Several criticisms target the measurement methods rather than the devices themselves. The sharpest one is found in a 2025 study dealing with ferroelectric non-volatile capacitors using oxide channels. Characterization of such devices had traditionally been done by slowly sweeping voltage up and down over a scale of several seconds. However, in actual memory arrays, devices operate with short pulses. When the authors systematically investigated write and reliability characteristics using the pulse method, they found that different things were required for the two states. The authors propose that to maintain the on state, it is important to optimize the degree to which polarization spontaneously relaxes, and to maintain the off state, it is important to reduce losses when reading with a time lag after writing. That nondestructive reading is maintained even under read stress exceeding 10⁹ cycles at 1 volt was also demonstrated under these pulse conditions (arXiv:2512.16040, device measurement).

There are several critiques pointing in the same direction. These are that comparing candidates requires placing density, read, write, and reliability alongside their application context (arXiv:2109.01188); that moving the stage to optical circuits adds yet another axis (arXiv:2606.01463); and that because real devices are rare, simulators remain at the center of exploration (arXiv:2502.10167). None of these tell us which one won; all of them tell us how we must measure to answer that question.

A Competition of Fixing Weaknesses and Dodging Them

The story of next-generation memory is far from a straight race toward a single correct answer. Electron spin, phases of matter, resistance changes, and ferroelectric polarization each chase the same dream through different physics. There are results that directly reduce weaknesses. Examples include the SOT cell that cuts terminals in half, the phase-change material that eliminates composition issues with a single element, and reads that overcome speed limits with shorter pulses. Designs that leave weaknesses alone and dodge them are just as noticeable. If writing is slow, they store only data with little writing; if flipped probabilistically, they draw random numbers with that probability; if definitions waver, they put those definitions themselves on the test bench.

Among the studies covered in this article, there was no winner, and in the end, there may not be just one. Several of the studies cited in this article were creating not only new devices, but also scales to properly compare those devices.

Source Papers

• "AERO" (2024) — arXiv:2404.10355 (preprint) — Tailoring erase time to the cell, lifespan +43%.
• "NVMExplorer" (2021) — arXiv:2109.01188 (preprint) — Measuring the trade-offs of embedded NVM.
• "RAIDR 회고" (2023) — arXiv:2306.16024 (preprint) — Dividing refresh cycles per row.
• "RowPress" (2023) — arXiv:2306.17061 (preprint) — Flipping just by keeping it open too long.
• "Producer-Consumer" (2024) — arXiv:2401.16279 (preprint) — The biggest barrier is information blocking.
• "3D NAND Lifetime" (2018) — arXiv:1807.05140 (preprint) — Three new error sources, 1.85 times or 78.9%.
• "PDA-LSTM" (2025) — arXiv:2511.00075 (preprint) — Reducing QLC error rate with page arrays.
• "NVMM 서베이" (2020) — arXiv:2010.04406 (preprint) — Hybrid, not replacement.
• "Modeling Emerging Memory" (2025) — arXiv:2502.10167 (preprint) — Simulators because devices are rare.
• "True Random Number… MRAM" (2021) — arXiv:2104.00198 (preprint) — True random numbers via stochasticity.
• "Two-terminal SOT-MRAM" (2018) — arXiv:1806.09713 (preprint) — Two-terminal cell, threshold current 70%↓.
• "Orbit-transfer torque" (2023) — arXiv:2312.01269 (preprint) — Field-free switching.
• "FUSE" (2019) — arXiv:1903.01776 (preprint) — Packing only blocks with few writes.
• "Phase change memory" (2010) — arXiv:1001.1164 (preprint) — Basis of maturity and list of tasks.
• "Optically-Controlled PCM" (2021) — arXiv:2107.11516 (preprint) — The price is structural redesign.
• "Monatomic PCM" (2019) — arXiv:1902.00254 (preprint) — Eliminating compositional drift with a single element.
• "Projected mushroom PCM" (2021) — arXiv:2105.13693 (preprint) — Operating principle of the projected structure.
• "Conduction Channel Formation" (2017) — arXiv:1701.00864 (preprint) — Observing pathways and oxygen rings.
• "Switching at 1.5 K" (2019) — arXiv:1908.05545 (preprint) — Switching down to cryogenic temperatures, ION/IOFF 84.
• "…memories are not memristors" (2019) — arXiv:1909.07238 (preprint) — Tested and found not to be.
• "Charged Oxygen Vacancy…" (2021) — arXiv:2106.12159 (preprint) — The culprit is the charge state of the vacancy.
• "Charge Balance in Fe-FETs" (2021) — arXiv:2105.12892 (preprint) — The bottleneck is the interface and dielectric layer.
• "20 ps Read in HfO2/ZrO2" (2026) — arXiv:2606.03677 (preprint) — 20 ps pulses when the window collapses.
• "FeFET Differential Bit-Cell" (2026) — arXiv:2606.19918 (preprint) — A 4T cell combining both modes.
• "Volatile Memory in HZO" (2025) — arXiv:2508.08973 (preprint) — Deliberately creating volatility.
• "Pulse-Mode nvCAPs" (2025) — arXiv:2512.16040 (preprint) — Measuring oxide channel devices in pulse mode.
• "Memristors — from In-memory…" (2020) — arXiv:2004.14942 (preprint) — Algorithms must be developed alongside.
• "In-memory hyperdimensional" (2019) — arXiv:1906.01548 (preprint) — Demonstration on 760,000 devices.
• "Opto-electronic Memories" (2026) — arXiv:2606.01463 (preprint) — The limit of optical circuits is the lack of usable memory.
• "Ultrafast flash… vdW" (2020) — arXiv:2009.01581 (preprint) — Roughly 20 ns via atomic-thickness stacking.